JPH0341322Y2 - - Google Patents

Description

[Detailed description of the invention] [Background] The invention relates to a videotape recorder (VTR), and in particular has a noise reduction circuit.
It is related to VTR. For home VTRs, the recording time is longer,
Therefore, as the tape speed decreases, the frequency band for audio recording becomes narrower, resulting in unsatisfactory sound quality. Therefore, the β system and VHS system each have their own noise reduction (NR) system to compensate for the deterioration in sound quality. these
A feature of the NR system is that it requires an encoder that compresses the audio signal during recording and a decoder that expands it during playback. Therefore, a magnetic tape recorded using these NR systems will have no effect unless it is played back using the same NR system, and conversely, a tape recorded using an NR system can be played back without using the NR system. As a result, the high frequency output is reduced and the sound quality deteriorates. Recently, VTRs that have multiple NR systems and can switch between them have also been considered. The present invention was developed in view of the above points, and it records an NR control signal on the control track during recording, and automatically determines whether or not the NR system is being used, and its type, based on this signal during playback. This paper proposes a magnetic recording/reproducing machine that controls the NR circuit by using [Key points of the invention] In this invention, considering that only the rising part of the control signal used in the servo system in a VTR is used, the duty ratio of the control signal is changed to create a control signal that has a rising and falling part. A signal portion and a noise reduction control signal having only a falling portion in the form of a triangular wave that is associated with the control signal portion at a predetermined time are recorded on a control track. During reproduction, this noise reduction control signal is used to automatically determine whether a noise reduction circuit was used during recording, or to determine the type of noise reduction used. [Example] The present invention will be described below with reference to the drawings. Figure 1 is a circuit block diagram of the signal generation circuit during recording, Figure 2 is a waveform diagram of the main part of Figure 1, Figure 3 is a circuit block diagram of the signal processing circuit during reproduction, and Figure 4 is Figure 3. FIG. In Figure 1, 1 is an input terminal that receives a vertical synchronization signal separated from the video signal, 2 and 3 are flip-flops (FF) triggered by the vertical synchronization signal, and FF3 is a 30Hz square wave (duty 50%). ), and the output of FF2 serves as one input of AND gate 4. 5 is an oscillator and a counter 11 composed of FF6 to FF10.
Outputs the clock. The outputs A to E of each stage of the counter 11 are used to create the NR control signal.
For the purpose of synchronizing with the vertical synchronizing signal, the output of the AND gate 4 resets FFs 6 to 10 of the counter 11 via an inverter 12 and a reset pulse generating circuit 13 . The reset pulse generating circuit 13 includes an inverter 14, a time constant circuit 15 including a resistor and a capacitor, and a NAND gate 16. The output of the gate pulse F generating circuit 17 is connected to the other input of the AND gate 4. The gate pulse generation circuit 17 is an AND gate 18,1
9 and an OR gate 20 which receives the outputs of both AND gates 18 and 19, and the AND gate 19 is
The AND gate 18 inputs the Q output of FF9 and the Q output of FF10, and the output of FF9 and the output of FF10. The Q output of FF7 is applied to the reset terminal of FF2 via a reset pulse generating circuit 21 similar to the reset pulse generating circuit 13 . 22 is a decoder circuit which inputs the output of each stage of the counter 11 and outputs a pulse having a predetermined time relationship with the vertical synchronizing signal;
It consists of an OR gate 25 which takes four outputs as input, and a NAND gate 26 which takes the output of the OR gate as one input. The AND gate 23 includes the Q output of FF7 (waveform B in Figure 2), the Q output of FF8 (waveform C in Figure 2),
FF9 output, FF10 output and switch
A first instruction signal from SW ₁ (inverted by inverter 27) is connected. and gate 2
4, the Q output of FF7 (Figure 2B), the output of FF8, the Q output of FF9 (Figure 2D), the output of FF10, and the second instruction signal from switch _W2 (inverted by inverter 28). It is connected.
The Q output of the FF6 (FIG. 2A) is connected to the remaining inputs of the NAND gate 26 of the decoder circuit. The output of the NAND gate 26 (K in FIG. 2) of the decoder circuit 22 is input to a bootstrap circuit 29 to generate a triangular wave, and its output is input to an adder 30. The output of the AND gate 4 (FIG. 2G) including the control signal section is input to the adder 30 through an amplifier 31. Next, the operation during recording will be explained according to FIGS. 1 and 2. The outputs of each stage of the counter 11 (A to E in FIG. 2, some of which are inverted) are applied to the decoder circuit 22 , and when the counter 11 is in a predetermined state when an instruction signal is output, A signal J having a high level is obtained. The signal J is NANDed with the output A, is converted into a signal K which becomes low level in a predetermined state, and is inputted to the bootstrap circuit 29 to obtain a triangular wave signal L. 1st instruction by switch SW ₁ and SW ₂ , 2nd instruction
The instruction signal is output when the first switch SW ₁ is turned on when the β-NR circuit is used during recording, and when the second switch SW ₂ is turned on when the Dolby NR circuit is used. Although they are not output simultaneously, for convenience of explanation, the waveforms of both instruction signals are shown in FIG. 2. Since two types of NR circuits are not used at the same time, it is desirable that the switches SW ₁ and SW ₂ be configured so that when one is on, the other is always off.
Also, the present invention is not limited to having two types of NR circuits, but only one type (for example, β-NR), and the remaining switches are used for other purposes (such as speed switching) or are not used at all. It can also be applied in cases. It is preferable that the first and second switches operate in conjunction with a switch or the like that instructs the use of the NR circuit during recording. The vertical synchronization signal input to terminal 1 is FF2 and
FF3 is triggered, and a 30Hz square wave (Fig. 2 I) is generated at terminal 32. The output of the other FF2 is ANDed with the signal F as described later, and since the FF2 is reset at the timing of the output B, it has a waveform like the signal G, which is added to the signal L to become the signal M. Gate pulse F applies a gate to every other 60 Hz vertical synchronizing signal, and as a result, signal G is given to reset pulse generating circuit 13 at a timing of 30 Hz. The reset pulse generating circuit 13 outputs a short reset pulse _R1 to the remote terminals of FF6 to FF10 when the input signal falls. Therefore, the counter 11 is synchronized with the vertical synchronization signal at a period of 30 Hz. Since the Q output of FF7 (FIG. 2B) is applied to the reset terminal of FF2 via the reset pulse generating circuit 21, signal G is obtained. As mentioned above, during recording, the counter 11 that counts the clock (960 Hz) from the oscillator 5 is reset with the vertical synchronization signal and synchronized with the vertical synchronization signal.
The output of each stage of the counter 11 is decoded to create a triangular wave-shaped signal having a falling portion in a predetermined relationship with the control signal portion. On the other hand, the rise of the control signal section matches the vertical synchronization signal,
The falling edge is defined by the output of the counter 11 , and a signal whose time relationship with the NR control signal portion described above is as shown in FIG. 3M is recorded on the control track of the VTR. Next, the circuit during reproduction will be explained with reference to FIG. Reference numeral 33 is a terminal for inputting a reproduction signal from the control head, and is connected to an amplifier 34. 3
5 is a separation circuit that separates the reproduced signal from the control head (Fig. 4a) into a positive polarity part and a negative polarity part, and the separated positive polarity signal (i.e., the rising part of the control signal part) is a monostable multi-channel circuit. A negative polarity signal (the falling portion of the control signal portion and the falling portion of the NR control signal) is applied to the pipelator (MM) 36 and to the MM 37 to trigger each MM. The output of MM37 (FIG. 4c) and the output of MM36 (FIG. 4b) are connected as inputs of NAND gate 38. The output of NAND gate 38 is applied to a reset pulse generating circuit 39 similar to that of FIG. 1 to generate a reset pulse for counter 11' (FIG. 4d). The reset pulse (Fig. 4d) is applied to the counter 11'
It is applied to the reset terminals of FFs 6 to 10 that make up the circuit. A signal from an oscillator 5 (same as that in FIG. 1) is input as a clock to the counter 11', and the output of each stage of the counter 11' is supplied to a decoder circuit 40. The decoder circuit 40 is composed of 4-input AND gates 41 and 42, and the AND gate 41 includes the output of FF7, the Q output of FF8, and the output of FF8.
The output of FF9 and the output of FF10 are inputted, and the output of FF7, the output of FF8, the Q output of FF9, and the output of FF10 are inputted to the AND gate 42. The output of AND gate 41 is connected to the input of AND gate 43, and the output of AND gate 42 is connected to the input of AND gate 44. The remaining inputs of AND gates 43 and 44 are connected to the output of MM 37 (which is triggered by a negative polarity signal). The outputs of AND gates 43 and 44 are applied to conversion circuits 45 and 46 , respectively. Conversion circuit 45 ,
Since the configuration of 46 is the same, the conversion circuit 45 connected to the AND gate 43 will be explained. and gate 4
The output of 3 is divided into two and one is connected to inverter 4.
It is connected to FF48 via 7. the other one is FF
AND gate 4 with 48 Q and output as inputs
9,50. and gate 49,
The outputs of MM 50 are connected to MMs 51 and 52, respectively, and the outputs of both MMs 51 and 52 are applied to OR gate 53 and connected to NR discrimination output terminal 54. Next, explanation will be given according to the main waveform diagram of FIG. 4. The reproduction signal of the control head (Fig. 4a) has both positive and negative polarities as shown in the figure, but the separation circuit 3
The positive polarity signal and negative polarity signal are separated by MM
36 and 37, signals as shown in FIGS. 4b and 4c are obtained. In order to discriminate the NR control signal, it is necessary to synchronize the counter 11' and the reproduced signal a. For this synchronization, the counter 11' is reset at the falling timing of the control signal portion of the reproduction signal a. To generate this reset pulse, a reset pulse generation circuit is driven by the NAND output of signals b and c. As the output of each stage of counter 11'
The Q outputs of FF7 to FF10 are connected to the fourth signal as signals e to h.
As shown in the figure. During playback, unlike during recording, the falling edge of the control signal portion is used as a reference for signal discrimination, so the signal output to the decoder circuit 40 is different from that during recording. AND gates 41 and 42 of decoder circuit 40
The output of the AND gate 43 is used as a gate pulse.
44, and if the NR control signal is recorded at the time of recording (in Fig. 4, for convenience, the first and second
A pulsed discrimination signal i or j (in which the NR control signal is displayed) is output. The pulse-like discrimination signals i and j pass through conversion circuits 45 and 46 , and the final discrimination signals of low level or high level are output to terminals 54 and 5.
4', and the NR circuit is controlled. The conversion circuit 45 is configured so that the high level periods of the two MMs 51 and 52 overlap, using the Q output and the output of the FF 48, whose states are inverted every time the pulse-like discrimination signal j is input. A high level signal is output. Note that some kind of storage means can of course be used in this conversion circuit portion. FIG. 5 is a circuit diagram of an additional circuit when the VTR is provided with an after-recording function, and FIG. 6 is a diagram showing the configuration of the control/audio head at that time. Further, the waveforms in FIG. 5 are shown in FIG. 2 N, O, and G'. During dubbing, it must be possible to determine whether the NR system was used to record the audio at the time of dubbing. Therefore, since it is necessary to erase the previously recorded NR control signal, the control track has an erase head (CE) as shown in FIG. During dubbing, the signal on the previously recorded control track is played back by the playback head (CP), the signal is erased by the subsequent erase head (CE), and the control signal and NR control signal are newly recorded by the recording head (CR). Record. Since it is necessary to match the phase of the newly recorded control signal with the phase of the previous control signal, the time t (th) corresponding to the distance X and tape speed V between the playback head (CP) and the recording head (CR) The circuit of FIG. 5 is provided with means for delaying the reproduced signal by an amount (see FIG. 2). A signal from the reproduction head (CP) is applied to a terminal 55, amplified by an amplifier 56, and supplied to a positive/negative polarity separation circuit 57, where only the positive polarity pulse (N in FIG. 2) is supplied to the MM 58. MM58 is the above-mentioned delay means and is the output of the next stage MM59 (second stage).
This is to delay the rise of the signal O) by a predetermined time t (=X/V). The output of MM59 (G' in Figure 2) is applied to AND gate 60, and the output of MM59 is applied to OR gates 61 and 62 only when the third switch SW ₃ is on (during dubbing). . The OR gate 61 is given the output of the AND gate 4 in FIG.
1 is applied to the inverter 12 in FIG.
Create a reset pulse. The output of AND gate 4 is applied to OR gate 61 via AND gate 63, and the output of AND gate 4 is output from OR gate 62 only when the fourth switch SW ₄ is on (normal recording). Since the configuration is as described above, the fourth switch _SW4 )
When is on, that is, during normal recording, the counter 11 is output by the output of the AND gate 4, as in the circuit shown in FIG.
is reset. On the other hand, when the third switch _SW3 is on, the signal of the reproduced control track is delayed for a predetermined period of time, and the counter is reset with the delayed signal. Output of MM59 (Fig. 2
The positive period of G') is set to be the same as the output of G in FIG. In FIG. 6, AE is an audio erasing head and A _PR is an audio recording/reproducing head. [Effects] According to the present invention, it is possible to automatically determine at the time of playback whether the NR circuit was used or not during recording of audio, and it is possible to prevent deterioration of sound quality due to incorrect use of the NR circuit. Furthermore, since the NR control signal is written on the control track while adhering to the current standards, there is no need for a new recording head, and discrimination can be made by adding an electronic circuit, which is practical.

[Brief explanation of the drawing]

The drawings are all related to the present invention; Fig. 1 is a circuit diagram of a circuit used during recording, Fig. 2 is a waveform diagram of the main part of Fig. 1, and Fig. 3 is a circuit diagram of a circuit used during reproduction. FIG. 4 is a waveform diagram of the main part of FIG. 3. Fifth
This figure is a circuit diagram of a circuit added to FIG. 1 when an after-recording function is provided, and FIG. 6 is a diagram showing the configuration of a control/audio head when an after-recording function is provided. Explanation of main figure numbers, 2, 3, 48, 48'...flip-flop, 5...oscillator, 11 , 11' ...
...Counter, 13 , 21, 39 ...Reset pulse creation circuit, 17...Gate pulse creation circuit, 2
2, 40 ...decoder circuit, 29 ...bootstrap circuit, 30...adder, 35...positive/negative separation circuit, 36, 37, 51, 51', 52, 52'...
...monostable multi.

Claims (1)

[Scope of utility model registration request] A video tape recorder equipped with a noise reduction circuit includes a counter that is reset by a vertical synchronizing signal and counts a predetermined clock signal, and a rising edge coincides with the vertical synchronizing signal and a falling edge coincides with the vertical synchronizing signal based on the vertical synchronizing signal and the counter output. means for outputting a control signal portion defined by the counter output; and means for decoding the counter output to create a triangular wave-shaped control signal portion having a falling portion in a predetermined relationship with the control signal portion; Adding means for adding the control signal part and the control signal part; means for recording the output of the adding means on a control track during recording; a counter for counting a predetermined clock signal; and a counter for decoding this counter means to extract the falling part of the triangular wave-shaped control signal contained in the reproduced signal and converting it into at least a noise reduction control signal. A videotape recorder comprising means for converting.