JPH0341773A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, particularly LDD (light
The present invention relates to a MOS transistor with a lydoped drain structure and a method of manufacturing the same.

[Summary of the invention]

The present invention provides a MOS transistor having an LDD structure.
The gate electrode is formed of a first gate electrode and a second gate electrode integrally formed on the side wall of the first gate electrode, and a low concentration impurity region is formed only under the second gate electrode on the drain side.
By forming a high concentration impurity region in self-alignment with the gate electrode, it is possible to lower the resistance on the source side and improve the current driving ability of the transistor, and to reduce the carrier concentration on the surface of the low concentration impurity region on the drain side. Initial deterioration is improved by controlling with the second gate electrode.

The present invention provides a method for manufacturing a MOS transistor, in which a low concentration impurity region is formed on the drain side through a mask layer that straddles a first gate electrode on a semiconductor substrate and covers the source side.
Next, a second gate electrode is integrally formed on the side wall of the first gate electrode, and high concentration impurities are introduced using the first and second gate electrodes as masks to form a high concentration impurity region, thereby achieving high current drive capability and MO with LDD structure with little initial deterioration
This makes it possible to easily manufacture an S transistor.

Further, in the above manufacturing method, the low concentration impurity region and the high concentration impurity region are formed with impurities of the first conductivity type, and the second conductivity type channel MOS transistor type region is masked with a mask layer used when forming the low concentration impurity region. , it is possible to manufacture a C-MOS transistor having the above-mentioned LDD structure without increasing the number of masks.

The present invention provides a MOS transistor having an LDD structure.
A gate electrode is formed on the side wall of the stepped portion of the semiconductor substrate, and high concentration impurity is applied in self-alignment with the gate electrode on the upper and lower steps of the stepped portion!
! 73? By forming the J region and forming a low concentration impurity region under the upper high concentration impurity region, it is possible to improve the current driving ability of the transistor as described above and to improve initial deterioration. This is what I did.

The present invention provides a MOS transistor having an LDD structure.
A gate electrode is formed on the side wall of the step portion of the semiconductor substrate, a high concentration impurity region is formed on the upper step of the step portion, a low concentration impurity region is formed in self-alignment with the gate electrode under the step portion, and a low concentration impurity region is formed on the side wall of the gate electrode. By forming a high concentration impurity region in self-alignment with the layer, the resistance on the source side is lowered and the current driving ability of the transistor is improved.

The present invention provides a MOS transistor having an LDD structure.
An L-shaped gate electrode is formed on the side wall of the stepped portion of the semiconductor substrate, and high concentration impurity regions are formed in self-alignment with the gate electrode at the upper and lower portions of the stepped portion, and the sides of the gate electrode that are in close contact with the side walls of the stepped portion are formed. By forming a low concentration impurity region under the step in a self-aligned manner with the step, the current driving ability of the transistor is improved in the same way as described above, and initial deterioration is improved.

[Conventional technology]

In MOS transistors, an LDD structure is generally used to prevent deterioration of transistor characteristics (i.e., changes in threshold voltage over time, deterioration of mutual conductance, etc.) due to hot carriers caused by miniaturization of channel length. There is.

As shown in FIG. 6, a conventional MOS transistor with an LDD structure has a gate electrode (3) formed on a semiconductor substrate of a first conductivity type, such as a p-type silicon substrate (1), with a gate insulating film (2) interposed therebetween. Then, using this gate electrode (3) as a mask, a second
Low concentration impurity regions (4a) and (5a) of conductivity type, that is, n-type.
) and then SiO2 on the side walls of the gate electrode (3).
An insulating sidewall part (6) is formed, and using this as a mask, n-type high concentration regions (4b) and (5b) are formed to form a source region (4) and a drain region (5), respectively. configured. (7) is an element isolation region formed by selective oxidation (LOGO3).

As shown in FIG. 7, as a manufacturing method for a MOS transistor with a short channel length, a stepped portion is formed on a p-type silicon substrate (15), and a gate electrode is formed on the side wall of the stepped portion via a gate insulating film (16). A polycrystalline silicon film (9) is selectively formed as shown in FIGS. A and B), and second conductivity type impurities are ion-implanted using this polycrystalline silicon film, that is, the gate electrode (9) as a mask, to form the upper step portion. N'' layers (10) and (l()) which will become the source and drain, respectively, are formed below the step (FIG. C), and then an insulating film (12) and an extraction electrode (1) are formed.
3) and (14) are known (see figure D) (see Japanese Patent Publication No. 61-60589).
.

[Problem to be solved by the invention]

In the above-mentioned conventional MO3I-transistor having the LDD structure (see FIG. 6), low concentration impurity regions (4a) and (5a) are provided in the source region (4) and drain region (5), respectively. The low concentration impurity region (5a) on the drain region (5) side is necessary to weaken the electric field strength and suppress the generation of hot carriers, but the low concentration impurity region (4a) on the source region (4) side is unnecessary. It is. Conventionally, this low concentration impurity region (4a) on the side of the source region (4)
The source resistance increased, and the current driving ability of the MOS transistor with the LDD structure decreased.

In addition, the low concentration impurity region (5a) of the drain region (5)
Hot carriers injected into the upper insulating films (2) and (6) reduce the carrier concentration on the surface of the low-concentration impurity region (5a), resulting in an increase in initial deterioration (value of initial Δgm/gmo). there were.

In view of the above-mentioned points, the present invention is directed to a semiconductor device, that is, an LD, which improves current drive capability and can improve initial deterioration.
The present invention provides a D-structure MOS transistor and a method for manufacturing the same.

[Means to solve the problem]

The semiconductor device (36) of the present invention includes a first gate electrode (2) on a semiconductor substrate (21) via a gate insulating film (24).
6A) and a second gate electrode (26B) integrally formed on the side wall of the first gate electrode (26A), and the second electrode (26B) on the drain side.
A low concentration impurity region (32) is formed only in the lower semiconductor substrate (21).
a), and a high concentration impurity region (31
) and (32b).

Further, the method for manufacturing a semiconductor device of the present invention includes a semiconductor substrate (
21) Forming a mask layer (28) covering the source side and having an opening (27) on the drain side over the first gate electrode (26A) formed above, and forming a low concentration impurity region (28) on the drain side. 32a) and forming a second gate electrode (268A) on the side wall of the first gate electrode (26A).
) and the step of integrally forming the first gate electrode (26A).
The second gate electrode (26B) is used as a mask to introduce high-concentration impurities to form high-concentration impurity regions (31) and (32b) that will become the source and drain.

Furthermore, in the above manufacturing method, the low concentration impurity region (32a
) and the high concentration impurity region (32b) are formed with impurities of the first conductivity type, and the M of the channel of the second conductivity type is formed by the mask layer (28) used when forming the low concentration impurity region (32a).
The OS transistor formation region (43) may be masked.

Another semiconductor device (51) of the present invention includes a semiconductor substrate (21).
) A gate electrode (49G) is formed on the side wall (4, 8C) of the stepped portion (4th day) through a gate insulating film (24), and gate electrodes are formed on the upper (48A) and lower (48B) of the stepped portion. Forming high concentration impurity regions (32b) and (31b) which become drains and sources in self-alignment with the electrode (49G),
At least the upper stage (48A) high concentration impurity region (32b
) is formed by forming a low concentration impurity region (32a) underneath.

Another semiconductor device (54) of the present invention includes a semiconductor substrate (21
) is formed on the side wall (48C) of the step part with a gate insulating film (2
A gate electrode (49G) is formed through the gate electrode (49G), and a high concentration impurity region (3
1), and a gate electrode (4
A low concentration impurity region (32a) is formed in self-alignment with the layer (53) formed on the side wall of the gate electrode (49G), and a high concentration impurity region (32b) which becomes a drain is formed in self-alignment with the layer (53) formed on the side wall of the gate electrode (49G). Configure.

Another semiconductor device (57) of the present invention includes a semiconductor substrate (21).
) A gate insulating film (2
4) Form an L-shaped gate electrode (49G) through the
High concentration impurity regions (31) and (32b) which will become the source and drain are formed in the upper step (48A) and the lower step (48B) of the gate electrode (49G) in self-alignment with the gate electrode (49G). The side that is in close contact with the side wall of the step part (4
A low concentration impurity region (32a) is formed at the lower step (48B) of the step in a self-aligned manner with 9a).

[Effect]

In the semiconductor device W (36) of the first invention, the low concentration impurity region (32a) is formed only on the drain (32) side and there is no low concentration impurity region on the source (31) side. 31) side resistance is reduced, and the transistor current driving ability is increased. Further, a first gate electrode (2) is formed on the low concentration impurity region (32a) on the drain (32) side.
Since the second gate electrode (26B) is formed integrally with the second gate electrode (26B), the carrier concentration on the surface of the low concentration impurity region (32a) can be controlled by this gate electrode (26), and initial deterioration is small. Become.

Further, in the manufacturing method of the second invention, a mask layer (26A) covering a part of the first gate electrode (26A) and covering the source side is used.
8) and introduce a low concentration impurity to form a low concentration impurity region (32a), and then form a first gate electrode (26A).
) is formed on the side wall of the first gate electrode (26B).
High concentration impurities are introduced using the second gate electrodes (26A) and (26B) as masks to form high concentration impurity regions (31)/l and (32b) that will become the source and drain. No low concentration impurity region is formed on the side, and a low concentration impurity region (32) is formed only on the drain (32) side.
2a) is formed, and a gate electrode (26) is formed on the low concentration impurity region (32a) on the drain side.
The semiconductor device (36) can be easily manufactured.

Furthermore, according to the manufacturing method of the third invention, the low concentration impurity region (32a) and the high concentration impurity region (31), (32b
) is formed with impurities of the first conductivity type, and the second conductivity type is formed using the mask layer (28) used when forming the low concentration impurity region (32a).
MO3I-transistor formation region (43
), it is possible to easily form a C-MOS transistor (complementary MO3 transistor) having the structure according to the first invention without increasing the number of masks.

In the semiconductor device (51) of the fourth invention, the semiconductor device (3
2> is formed, and a source (31) is formed in the lower stage (48B). In the source (31) at the bottom of the step, no low concentration impurity region in contact with the channel region (50) is substantially formed, and only in the drain (32) at the top of the step, the low concentration impurity region (32a) in contact with the channel region is not formed. ) is formed, so the current driving ability of the transistor is increased.

Also, the low concentration impurity region (32a) of the drain (32)
Since the gate electrode (49G) is formed on the side wall of the stepped portion facing the gate insulating film (24), the carrier concentration on the surface of the low concentration impurity region (32a) can be adjusted to
G), and the initial deterioration is reduced. In addition, since the drain (32) is formed at the upper level of the stepped portion and the source (31) is formed at the lower level, the drain (32)
The depletion layer is difficult to extend from the source (31) side to the source (31) side, and bunch-through is therefore difficult to occur.

In the semiconductor device (54) of the fifth invention, the source (31) is provided at the upper step (48A) of the step in self-alignment with the gate electrode (49G) formed on the side wall (48C) of the step of the semiconductor substrate (21). A drain (32) is formed at the lower step (48B) of the step. Further, since there is no low concentration impurity region on the source (31) side, and there is a low concentration impurity region (32a) only on the drain (32) side, the current driving ability of the transistor can be increased.

In the semiconductor device (57) of the sixth aspect of the invention, the upper step (48
A source (31) is formed in the lower part of the step (48B).
) is formed with a drain (32). Then, an L-shaped gate electrode (4
Low concentration impurity region (32a) using the thickness difference of 9G)
is formed, and a low concentration impurity' is formed on the upper source (31) side.
Jf! Since the A region is not formed, the current driving ability of the transistor can be improved. In addition, the drain (32
) on the low concentration impurity region (32a) is a gate insulating film (
Since the gate electrode (49G) exists through 24),
The carrier concentration on the surface of the low concentration impurity region (32a) can be controlled, and initial deterioration can be reduced.

〔Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of an LDD structure MOS transistor according to the present invention. In this example, first, as shown in FIG. 1A, an element isolation region (Sing) (22) is formed by selective oxidation (LOCO5) on the main surface of a semiconductor substrate of conductivity type (2), for example, a P-type silicon substrate (21). ) is formed, and a gate insulating film (24) made of, for example, 5i02 is formed on the main surface of the element forming region (23). Then, the gate insulating film (
24) A first gate electrode (26A) made of polycrystalline silicon, for example, with a Si0g film (25) laminated on its upper surface is formed thereon.

Next, as shown in FIG. 1B, the first gate electrode (26A
), covering the region where the source region is to be formed and the opening (27
) A photoresist mask (28) is formed.

A low concentration second conductivity type impurity, that is, an n-type impurity (29) is ion-implanted through this photoresist mask (28).Next, after forming a polycrystalline silicon film on the entire surface, R
By TE (reactive ion etching), a sidewall portion (26B) made of a polycrystalline silicon film is formed on the sidewall of the first gate electrode (26^) as shown in FIG. 1C. This side wall portion (26B) is integrated with the first gate electrode (26A) and becomes a second gate electrode to which the same potential is applied.

These first and second gate electrodes (26A) and (26A)
B) constitutes the gate electrode (26). and,
This first gate electrode (26A) and the second gate electrode (
Using 26B) as a mask, high concentration n-type impurities (30) are ion-implanted to form source and drain regions.

Next, an annealing treatment for activation is performed to form an n-type source region (31) consisting of a high concentration impurity region, and an n-type drain consisting of a low concentration impurity region (32a) and a high concentration impurity region (32b). A region (32) is formed (see first diagram).

Next, a glabellar insulating film (33) is deposited, source and drain contact holes are formed, and after a reflow process, the source region (31) and drain region (32) are formed.
The source electrode (34
) and a drain electrode (35>) are formed.

In this way, the MO of the target LDD structure shown in the first diagram is
Obtain an S transistor (36).

The LDD structure MOS transistor (3
According to 6), the low concentration impurity region (32a) is formed only on the drain region (32) side and no low concentration impurity region is formed on the source region (31) side, so that the resistance on the source side is reduced. Current drive capability can be improved. In addition, the low concentration impurity region (3) of the drain region (32)
2a) On top is a second gate electrode integrated with the first gate electrode (26^).
Since the second gate electrode (26B) is formed, the low concentration impurity region (26B) is formed.
The carrier concentration on the surface of 32a) can be controlled,
Initial deterioration of the MOS transistor can be reduced.

Looking at the manufacturing process, we see that MOS with a normal LDD structure
Compared to the transistor, the low concentration n-type impurity (
This means that the number of resist masks (28) used for ion implantation (29) is increased by one. However, when applied to a C-MOS transistor, the number of masks does not increase. That is,
In the manufacturing process of C-MOS transistors, the eighth
As shown in the figure, for example, a p-type well region (42) is formed in a predetermined region of the -main surface of an n-type silicon substrate (41), and a p-type well region (42) and an n-type substrate (41) are formed. After forming gate electrodes (45) and (46) made of polycrystalline silicon films in the upper p-channel MOS transistor formation region (43) through a gate insulating film (44), for example, a p-channel MOS transistor type tc pJf is formed. The area (43) is covered with a photoresist mask (28) and the n-channel MO3
A low concentration n-type impurity (
29) is ion-implanted. Note that (22) is an element isolation region, and (25) is a 5iO1 film stacked on the gate electrode.

In the present invention, the photoresist mask (28) at this time is used as shown in FIG.
Extend it to the position where it straddles the top, and apply a low concentration of n only on the drain side.
A type impurity (29) is ion-implanted.

In this way, the process shown in FIG. 1B described above can be obtained,
A C-MOS transistor having the desired LDD structure shown in the first diagram can be manufactured without increasing the number of masks.

FIG. 3 shows another example of the present invention. In this example, the third
As shown in FIG. A, a step portion (48) having a predetermined step d is formed on the main surface of a semiconductor substrate of a first conductivity type, for example, a P-type silicon substrate (21). Then, an element isolation region (22) is formed by selective oxidation using the usual method, and the upper step part (22) is formed by selective oxidation.
48A), the side wall of the step part (48C) and the lower part of the step part (48C)
After forming a gate insulating film (24) of Sin or the like on the surface over 8B), a polycrystalline silicon film (49) which will become a gate electrode is deposited on the entire surface.

Next, the polycrystalline silicon film (49) is subjected to RIE (reactive ion etching) to leave the polycrystalline silicon film (49) only on the side walls of the stepped portion.
For example, phosphorus or the like is introduced into 9) by deposition to lower the resistance, thereby forming the gate electrode (49G) shown in FIG. 3B.

Next, as shown in FIG. 3C, using the gate electrode (49G) as a mask, low concentration n-type impurity (29) is ion-implanted deeply into the upper step (48A) and lower step (48B) of the stepped portion, and then,
As shown in the third diagram, a high concentration n-type impurity (30) is ion-implanted shallowly.

Thereafter, an annealing process for activation is performed, and n-type drain regions (32) are formed in self-alignment with the gate electrode (49G) at the upper (48A) and lower (48B) step portions, respectively.
and an n-type source region (31).

The drain region (32) is a shallow high concentration impurity region (32b
) and a low concentration impurity region (32a) below it,
Similarly, the source region (31) is a shallow high concentration impurity region (3
1b) and a low concentration impurity region (31a) below it (see Figure 3E). However, in this case, the area directly under the gate electrode (49G) at the bottom of the step is the substantial channel region (
50), only the drain region (32) has an LDD structure, and there is a low concentration impurity region (32a) in contact with the channel region (50), and in the source region (31), the channel region (50) is substantially This means that there is no low concentration impurity region in contact with.

Next, the glabellar insulating film (32) is formed, source and drain contact holes are formed, and after reflow treatment, the source electrode (34) and drain electrode (34) are formed using M.
35). In this way, the desired MOS transistor (51) having an LDD structure as shown in FIG. 3 is obtained.

An LDD structure MOS transistor (
According to 51), on the drain region (32) side at the upper stage of the stepped portion, the low concentration impurity region (32a) is connected to the high concentration impurity region (32a).
32b) Although the LDD structure is formed more deeply, the low concentration impurity region Mi (31a) is directly under the high concentration impurity region (31b) on the source region (31) side below the step, forming a channel. There is substantially no low concentration impurity region that is not in contact with the region (50).Therefore, the resistance on the source side can be lowered, and the current driving ability of the transistor can be improved.

In addition, a drain region (32) is formed at the upper level of the step, and a gate electrode (49G) is formed on the side wall of the step facing the low concentration impurity region (32a).
(49G) makes it possible to control the surface concentration, that is, the carrier concentration, of the low concentration impurity region (32a), and to reduce the deterioration caused by hot carriers, that is, the initial deterioration.

In addition, since the sidewalls of the polycrystalline silicon film formed by RIH are used as gate electrodes (49G) using the stepped portions, the gate length can be reduced, allowing the formation of fine MOS transistors. .

Furthermore, a drain region (32) is formed at the upper level of the step, and a channel region (50) and a source region (31) are formed at the lower level of the step.
), the depletion layer is difficult to extend from the drain region (32) to the source region (31), and punch-through is difficult to occur.

FIG. 4 shows still another embodiment of the present invention in which a stepped portion is similarly utilized, with a source region formed in the upper step and a drain region formed in the lower step. In this example,
As shown in FIG. 4A, a step portion (48) having a predetermined step d is formed on the main surface of a semiconductor substrate of a first conductivity type, for example, a p-type silicon substrate (21). Then, an element isolation region (22) is formed by selective oxidation using the usual method, and a gate insulating film made of SiO□ or the like is formed on the surface of the upper step (48A), the side wall of the step (48C), and the lower step (48B) of the step. After forming (24), a polycrystalline silicon film (49) which will become a gate electrode is deposited.

Next, by RIE, a polycrystalline silicon film (49) is left only on the side walls of the stepped portion, and phosphorus or the like is introduced into this polycrystalline silicon film (49) to lower the resistance, and the gate electrode (49G) shown in FIG. ) to form. And this gate electrode (
49G) as a mask, a low concentration n-type impurity (29) is ion-implanted into the upper stage (48A) and lower stage (48B) of the stepped portion.

Next, as shown in FIG. 4C, after forming a SiO□ film on the entire surface, RIE is performed on this SiO□1 film to form a SiO2 sidewall portion (53) on the sidewall of the gate electrode (49G). do. Then, this gate electrode (49G) and the
High concentration n-type impurity (30) is ion-implanted into the upper and lower steps of the stepped portion using the g-side wall portion (53) as a mask.

Thereafter, an annealing process for activation is performed to form an n-type source region (31) made of a highly doped impurity region at the upper step (48A) and at the lower step (48B).
) is formed with an n-type drain region (32) consisting of a low concentration impurity region (32a) and a high concentration impurity region (32b) (see the third diagram).

Next, a glabellar insulating film (33) is formed, source and drain contact holes are formed, and a reflow process is performed, followed by a source electrode (34) and a drain electrode (
35). In this way, a desired MOS transistor (54) having an LDD structure as shown in the fourth diagram is obtained.

An LDD structure MOS transistor with such a configuration <5
According to 4), the low concentration impurity region (32a) does not have a significant shape in the source region (31) above the step, and the low concentration impurity region (32a) is in contact with the channel region (50) only in the drain region (32) below the step. ) is expressed. Therefore, the resistance on the source side can be lowered, and the current driving ability of the transistor can be improved. In addition, as in the example shown in FIG.
G), the gate length can be reduced and a fine MOS transistor can be formed.

FIG. 5 shows yet another embodiment of the invention.

In this example, as shown in FIG. 5A, a semiconductor substrate of the first conductivity type, for example, a p-type silicon substrate (
A step portion (48) is formed on the main surface of the step portion (48A), an element isolation region (22) is formed by selective oxidation, and the upper step portion (48A) is formed on the main surface of the step portion (48A).
), step side wall (48G) and lower step (48B)
A gate insulating film (24
), a polycrystalline silicon film (49) that will become a gate electrode is formed over the entire surface along the stepped portion (48).

A low concentration n-type impurity (29) is then ion-implanted into the surface of the silicon substrate (21) through this polycrystalline silicon film (49). At this time, since the vertical thickness tl of the portion (49a) of the polycrystalline silicon film (49) in contact with the step side wall (48C) is larger than the thickness t2 of the other portion, the underlying substrate (21) The ions are not implanted, but ions are implanted only into the surfaces of the other upper step (48A) and lower step (48B).

Next, as shown in FIG. 5B, a polycrystalline silicon film (49) is formed.
An insulating film (56) such as 5i02 is deposited on the entire surface.

Next, as shown in FIG. 5C, R is applied to the insulating film (56).
The insulating film (56) is left only on the sidewall of the stepped portion of the crystalline silicon film (49) subjected to IE. Then, this insulating film (56
) as a mask for the upper step (48A) and lower step (4)
8B), a high concentration of n-type impurity is ion-implanted.

Thereafter, annealing is performed to form a source region (31) consisting of a high concentration impurity region in the upper step (48A) of the step of the silicon substrate (21), as shown in the fifth diagram, and then to form the source region (31) consisting of a high concentration impurity region in the lower step (48B) of the step. a drain region (32) consisting of a low concentration impurity region (32a) and a high concentration impurity region (32b);
form.

Next, as shown in FIG. 5E, the insulating film (56
) is used as a mask to selectively etch the polycrystalline silicon film (49). This selective etching leaves an L-shaped polycrystalline silicon film extending from the side surface to the bottom surface on the side wall of the stepped portion of the silicon substrate, and this becomes the gate electrode (49G).

Next, Zetsu! ! After removing l1l (56), a glabellar insulating film (33) is formed, source and drain contact holes are formed, and after reflow treatment, a source electrode (34) and a drain electrode (35) are formed using M. . In this way, the MO of the target LDD structure shown in FIG.
Obtain an S transistor (57).

According to the LDD structure transistor (57) having such a configuration, the low concentration impurity region (32a) is formed only on the drain region (32) side below the step, and the low concentration impurity region (32a) is formed on the source region (31) above the step. Since no impurity region is formed, the current driving ability of the transistor can be improved as in the case above. Furthermore, since a gate electrode (49G) is formed on the low concentration impurity region (32a) of the drain region (32), the carrier concentration on the surface of the low concentration impurity region (32a) is reduced by this gate electrode (49G). control, and initial deterioration can be reduced.

〔Effect of the invention〕

According to the semiconductor device of the present invention, a gate electrode consisting of a first and a second gate electrode is formed, a high concentration impurity region serving as a source and a drain is formed in self-alignment with the second gate electrode, and a drain Since a low concentration impurity region is formed only under the second gate electrode on the side, the resistance on the source side is lowered and the current driving ability of the LDD structure transistor can be improved. The carrier concentration on the surface of the concentrated impurity region can be controlled and initial deterioration can be reduced.

Further, according to the manufacturing method according to the present invention, a low concentration impurity region is formed on the drain side by covering the source side with a mask layer spanning the first gate electrode, and then a second impurity region is formed on both side walls of the first gate electrode. Since the gate electrode is integrally formed and the highly concentrated impurity region is formed using this gate electrode as a mask,
The above semiconductor device can be easily manufactured. Furthermore, in this manufacturing method, if the MOS transistor formation region of the second conductivity type channel is masked with the mask layer used when forming the low concentration impurity region on the MOS transistor side of the first conductivity type channel, the number of process steps, that is, the number of mask steps can be increased. A C-MOS transistor having the above structure can be easily formed without increasing the cost.

Further, according to the semiconductor device according to the present invention, the gate electrode is formed on the side wall of the step portion formed in the semiconductor substrate, and the high concentration impurity regions are formed in self-alignment with the gate electrode at the upper and lower steps of the step portion. In both cases, a low concentration impurity region is formed under the upper high concentration impurity region, so that the current driving capability of the transistor having the LDD structure can be improved and initial deterioration can be reduced. Further, the occurrence of bunch-through between the source and drain can be controlled, and furthermore, a fine transistor with a short channel length can be formed.

Further, according to the semiconductor device of the present invention, the gate electrode is formed on the side wall of the step formed in the semiconductor substrate, the high concentration impurity region is formed in the upper step of the step, and the high concentration impurity region is formed in the lower step of the step in self-alignment with the gate electrode. Since a low concentration impurity region is formed and a high concentration impurity region is formed in self-alignment with the layer formed on the side wall of the gate electrode, it is possible to improve the current driving ability of the transistor with the LDD structure, and also to shorten the channel length. It is possible to form small microtransistors.

Further, according to the semiconductor device of the present invention, an L-shaped gate electrode is formed on the side wall of the step formed in the semiconductor substrate, and high concentration impurity regions are formed in self-alignment with the gate electrode at the upper and lower steps of the step. However, since the a'-concentration impurity region is formed under the step in self-alignment with the side of the gate electrode that is close to the side wall of the step, it is possible to improve the current driving capability of the transistor having the LDD structure. Initial deterioration can be reduced.

[Brief explanation of drawings]

FIGS. 1A to 1D are cross-sectional views showing an example of a MOS transistor according to the present invention in the order of steps, and FIG.
3A-3E are cross-sectional views showing a process example when applied to a method for manufacturing a transistor, FIGS. 5A to 5F are cross-sectional views in the order of steps showing another example of the MOS transistor according to the present invention, and FIG. 6 is a cross-sectional view in the order of steps showing another example of the MOS transistor according to the present invention.
Cross-sectional views of OS transistors, Figures 7A-D are conventional MO transistors.
3I-Cross-sectional views in the order of steps showing an example of a transistor manufacturing method, No. 8
The figure is a cross-sectional view showing an example of a manufacturing method of a conventional C-MOS transistor having an LDD structure. (21) is a semiconductor substrate, (24) is a gate insulating film, (2
6) ((26A) (26B) ) is the gate electrode, (3
1) is the source region, (32) is the drain region, (32a
) is a low concentration impurity region, and (32b) is a high concentration impurity region.

Claims (1)

[Claims] 1. A gate electrode formed on a semiconductor substrate includes a first gate electrode and a second gate electrode integrally formed on a side wall of the first gate electrode.
a gate electrode, a low concentration impurity region is formed only on the semiconductor substrate under the second gate electrode on the drain side, and a high concentration impurity region is formed in self-alignment with the second gate electrode. A semiconductor device consisting of 2. Forming a mask layer covering the source side and having an opening on the drain side over the first gate electrode formed on the semiconductor substrate; Forming a low concentration impurity region on the drain side; a step of integrally forming a second gate electrode on a side wall of the first gate electrode; and forming a high concentration impurity region by introducing a high concentration impurity using the first gate electrode and the second gate electrode as masks. A method for manufacturing a semiconductor device, comprising the steps of: 3. In claim 2, the low concentration impurity region and the high concentration impurity region are formed of impurities of a first conductivity type, and a mask layer used when forming the low concentration impurity region forms a second conductivity type channel. A method for manufacturing a semiconductor device, comprising masking a MOS transistor formation region. 4. A gate electrode is formed on a side wall of a step formed in the semiconductor substrate, and high concentration impurity regions are formed in self-alignment with the gate electrode at the upper and lower stages of the step, at least below the upper high concentration impurity region. A semiconductor device in which a low concentration impurity region is formed. 5. A gate electrode is formed on a side wall of a step formed in the semiconductor substrate, a high concentration impurity region is formed in the upper part of the step, and a low concentration impurity region is formed in self-alignment with the gate electrode in the lower part of the step, A semiconductor device in which a high concentration impurity region is formed in self-alignment with a layer formed on a side wall of the gate electrode. 6. An L-shaped gate electrode is formed on the side wall of the step formed in the semiconductor substrate, and high concentration impurity regions are formed in self-alignment with the gate electrode at the upper step and the lower step of the step, and the gate electrode is A semiconductor device comprising a low concentration impurity region formed below the step in self-alignment with a side close to the side wall of the step.