JPH0341962B2 - - Google Patents
Info
- Publication number
- JPH0341962B2 JPH0341962B2 JP6433682A JP6433682A JPH0341962B2 JP H0341962 B2 JPH0341962 B2 JP H0341962B2 JP 6433682 A JP6433682 A JP 6433682A JP 6433682 A JP6433682 A JP 6433682A JP H0341962 B2 JPH0341962 B2 JP H0341962B2
- Authority
- JP
- Japan
- Prior art keywords
- thermistor
- conductive
- thin film
- manufacturing
- conductive part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000000919 ceramic Substances 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 239000007772 electrode material Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000004043 responsiveness Effects 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Thermistors And Varistors (AREA)
Description
【発明の詳細な説明】
本発明は作業性容易にして応答性の優れたサー
ミスタを安価に提供しようとするサーミスタの製
造法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a thermistor that is easy to work with and provides a thermistor with excellent responsiveness at a low cost.
従来における薄膜サーミスタの製造は、印刷に
より電極が多数設けられたセラミツク板上に薄膜
サーミスタ層を蒸着する際に、それぞれの電極の
引出電極となる部分にマスクを使用してサーミス
タ層を蒸着しないようにしている。そして、この
ように形成されたものを１チツプづつ切断して製
造するものであつた。 In the conventional manufacturing of thin film thermistors, when a thin film thermistor layer is deposited on a ceramic plate on which many electrodes are printed, a mask is used on the part that will become the lead electrode of each electrode to prevent the thermistor layer from being deposited. I have to. The thus formed product was then cut into individual chips.
このような製造によるものは、電極の寸法精度
が製品の特性バラツキに大きく影響するものであ
つた。また、サーミスタ層の蒸着時にマスクを使
用するため、生産時の作業性も悪いといつた欠点
を有していた。 In products manufactured in this manner, the dimensional accuracy of the electrodes has a large effect on variations in the characteristics of the product. Furthermore, since a mask is used during vapor deposition of the thermistor layer, workability during production is also poor.
本発明は以上のような従来の欠点を除去するサ
ーミスタの製造法を提案するものであり、以下そ
の一実施例について第１図〜第７図と共に説明す
る。 The present invention proposes a method for manufacturing a thermistor that eliminates the above-mentioned conventional drawbacks, and one embodiment thereof will be described below with reference to FIGS. 1 to 7.
まず、図において１は熱伝導性に優れた厚み
0.1〜0.5mmのアルミナ板等のセラミツク基板で、
第１図に示すように多数の直径が0.1〜0.5mm程度
の穴２が整列状に開けられている。この基板１の
片面に、銀、パラジウム、金、白金またはこれら
を混合してなる電極材料を印刷し、この時に穴２
の中にその電極材料が流れ込み、完全に電極材料
が穴２を埋めるようにする。この状態を第２図に
示しており、上記基板１の片面に設けられた導電
部３は穴２内に達している。つぎに、上記基板１
のもう一方の面に上記と同じ電極材料を印刷し、
第３図に示すように導電部４を形成する。これに
より上記導電部３，４は多数の穴２を通して電気
的に完全な導通状態となる。ついで、上記基板１
の片面の上記導電部３上に第４図に示すように、
スパツタリングにより例えばSiCからなる薄膜サ
ーミスタ層５を形成する。なお、ターゲツトには
SiC焼結体（直径300mm、厚さ７mm）を用い、ス
パツタ圧力３×10-2〜５×10-2Torr、高周波電
力１〜2KW、基板温度500〜700℃、スパツタ時
間４〜８時間でスパツタリングを行う。 First, in the figure, 1 is the thickness with excellent thermal conductivity.
Ceramic substrate such as 0.1~0.5mm alumina plate,
As shown in FIG. 1, a large number of holes 2 having diameters of about 0.1 to 0.5 mm are formed in an array. An electrode material made of silver, palladium, gold, platinum, or a mixture of these is printed on one side of the substrate 1, and at this time, holes 2
The electrode material flows into the hole 2 so that the electrode material completely fills the hole 2. This state is shown in FIG. 2, in which the conductive portion 3 provided on one side of the substrate 1 reaches into the hole 2. Next, the above board 1
Print the same electrode material as above on the other side of the
A conductive portion 4 is formed as shown in FIG. As a result, the conductive parts 3 and 4 are completely electrically connected through the many holes 2. Then, the above substrate 1
As shown in FIG. 4, on one side of the conductive part 3,
A thin film thermistor layer 5 made of SiC, for example, is formed by sputtering. In addition, the target
Using a SiC sintered body (diameter 300 mm, thickness 7 mm), sputtering pressure 3×10 -2 to 5×10 -2 Torr, high frequency power 1 to 2 KW, substrate temperature 500 to 700°C, sputtering time 4 to 8 hours. Sputtering.
さらに、そのサーミスタ層５の上に上記と同じ
電極材料を印刷して、第５図に示すように導電部
６を形成する。その後、多数の穴２によつて上記
導電部３，４が導通している状態のものを第６図
に示すように切断線７のところで切断し、穴２の
１つでそれぞれ１チツプが導通している形に切断
する。このようにしてサーミスタは製造されるの
であり、第７図に１チツプになつた状態のサーミ
スタを示している。 Further, the same electrode material as above is printed on the thermistor layer 5 to form a conductive part 6 as shown in FIG. Thereafter, the conductive parts 3 and 4 are electrically conductive through the many holes 2, and cut at the cutting line 7 as shown in FIG. Cut it into the shape you want. The thermistor is manufactured in this manner, and FIG. 7 shows the thermistor in a single-chip state.
このような製造とすることによつて、セラミツ
ク基板として用いる例えばアルミナ板は薄く熱伝
導性に優れているため、応答性の優れたものとな
る。また、従来のようにマスクを使用しないため
位置合せの作業がなく、作業上の向上が図れる。 By manufacturing in this manner, the alumina plate used as the ceramic substrate, for example, is thin and has excellent thermal conductivity, so that it has excellent responsiveness. Furthermore, since a mask is not used as in the conventional method, there is no need for positioning work, which improves the work efficiency.
以上のように本発明の製造法によれば、熱伝導
性に優れたセラミツク基板の面に薄膜サーミスタ
層を形成することによつて、高品質で組立ての作
業性もきわめて優れたものとなり、安価にして製
作できるという実用的価値を有するものである。 As described above, according to the manufacturing method of the present invention, by forming a thin film thermistor layer on the surface of a ceramic substrate with excellent thermal conductivity, a high quality product with extremely excellent assembly workability and low cost can be achieved. It has practical value in that it can be manufactured by
第１図は本発明の製造法を説明するためのセラ
ミツク基板の斜視図、第２図〜第５図は同製造工
程順の状態を示す断面図、第６図は同じく切断工
程を示す斜視図、第７図は同じく切断によりサー
ミスタが１チツプになつた状態を示す斜視図であ
る。
１……セラミツク基板、２……穴、３，４……
第１、第２の導電部、５……薄膜サーミスタ層、
６……第３の導電部。
FIG. 1 is a perspective view of a ceramic substrate for explaining the manufacturing method of the present invention, FIGS. 2 to 5 are cross-sectional views showing the same manufacturing process, and FIG. 6 is a perspective view showing the cutting process. , and FIG. 7 is a perspective view showing the thermistor cut into one chip. 1... Ceramic substrate, 2... Hole, 3, 4...
First and second conductive parts, 5...thin film thermistor layer,
6...Third conductive part.
Claims (1)
ク基板の両面にその穴を通して印刷により第１、
第２の導電部を設け、上記セラミツク基板の片面
の上記導電部上にサーミスタ特性を有する材料を
蒸着して薄膜サーミスタ層を形成し、この薄膜サ
ーミスタ層の上に導電材料を蒸着または印刷して
第３の導電部を設け、その後多数の穴によつて上
記第１、第２の導電部が導通している状態のもの
を１ケの穴によつて導通している形に切断するこ
とを特徴とするサーミスタの製造法。1. The first,
A second conductive part is provided, a material having thermistor characteristics is deposited on the conductive part on one side of the ceramic substrate to form a thin film thermistor layer, and a conductive material is deposited or printed on the thin film thermistor layer. A third conductive part is provided, and the first and second conductive parts are then cut into a shape in which conduction is established through one hole. Characteristic manufacturing method of thermistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57064336A JPS58182202A (en) | 1982-04-16 | 1982-04-16 | Manufacturing method of thermistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57064336A JPS58182202A (en) | 1982-04-16 | 1982-04-16 | Manufacturing method of thermistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58182202A JPS58182202A (en) | 1983-10-25 |
| JPH0341962B2 true JPH0341962B2 (en) | 1991-06-25 |
Family
ID=13255292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57064336A Granted JPS58182202A (en) | 1982-04-16 | 1982-04-16 | Manufacturing method of thermistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182202A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01171201A (en) * | 1987-12-25 | 1989-07-06 | Okazaki Seisakusho:Kk | Thin film resistance temperature measuring body and temperature measuring body |
-
1982
- 1982-04-16 JP JP57064336A patent/JPS58182202A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58182202A (en) | 1983-10-25 |
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