JPH0342578U - - Google Patents
Info
- Publication number
- JPH0342578U JPH0342578U JP10357589U JP10357589U JPH0342578U JP H0342578 U JPH0342578 U JP H0342578U JP 10357589 U JP10357589 U JP 10357589U JP 10357589 U JP10357589 U JP 10357589U JP H0342578 U JPH0342578 U JP H0342578U
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- motherboard
- switch element
- input signals
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案の実施例のブロツク図、第２図
は本考案の実施例のマザーボードの詳細回路例を
示す。
１……被測定信号入力端子、２……マザーボー
ド、３……バツフア出力切換手段、４……制御信
号デコーダ及び選択制御回路、５……バツフア出
力端子、１ａ，２ａ，３ａ……ｎａ……バツフア
回路、１ｂ，２ｂ，３ｂ……ｎｂ……バツフアボ
ード、１ｃ，２ｃ，３ｃ……ｎｃ……スイツチ素
子。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of a motherboard according to an embodiment of the present invention. 1 ...Measurement signal input terminal, 2 ...Motherboard, 3 ...Buffer output switching means, 4...Control signal decoder and selection control circuit, 5...Buffer output terminal, 1a, 2a, 3a...na... Buffer circuit, 1b, 2b, 3b... nb... Buffer board, 1c, 2c, 3c... nc... Switch element.
Claims (1)
択接続するためのバツフア回路を搭載したバツフ
アボードを複数接続したマザーボードを設け、 該設けられたマザーボード上に、 前記バツフア回路のそれぞれの出力端にそれぞ
れ接続されたスイツチ素子と、 該スイツチ素子を制御するための制御信号デコ
ーダ及び選択制御回路とを有してなることを特徴
とする多チヤンネルバツフア回路。[Scope of Claim for Utility Model Registration] A motherboard to which multiple types of input signals are input and a plurality of buffer boards equipped with buffer circuits for selective connection according to each of the input signals is provided, The motherboard is equipped with a switch element connected to each output terminal of the buffer circuit, and a control signal decoder and a selection control circuit for controlling the switch element. Channel buffer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10357589U JPH0342578U (en) | 1989-09-05 | 1989-09-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10357589U JPH0342578U (en) | 1989-09-05 | 1989-09-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0342578U true JPH0342578U (en) | 1991-04-22 |
Family
ID=31652405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10357589U Pending JPH0342578U (en) | 1989-09-05 | 1989-09-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0342578U (en) |
-
1989
- 1989-09-05 JP JP10357589U patent/JPH0342578U/ja active Pending
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