JPH0342914A - Information converter - Google Patents

Abstract

PURPOSE:To prevent a peak shift from being exceeded and to improve the reliability by constituting a selecting means so that there are one-seven '0's is present between one optional '1' in a converted code sequence and the next '1' and the divergence range of DSV(Digital Sum Variation) is <=+ or -9 when (m)bit information is converted into an (n)-bit code (m<n). CONSTITUTION:When a hexadecimal information word 60 is inputted from an input terminal 3 to an encoder 4, the MSC output of the encoder 4 is Low, the LSB of the code word of the last converted information word is 1, and the output (a) of a gate 6 is Low. Further, a computing element 9 loads the last DSV=0 of the information word 60 and the code word which is thus selected in a parallel/serial converter 15 when a Symbol CLR 17 rises and they are outputted, bit by bit, in series every time a Channel CLR 18 rises.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to an information converter, particularly when converting a digital signal into a signal suitable for the recording device or transmission device when recording or transmitting a digital signal. The present invention relates to an information converter suitable for use in.

[Prior art] Conventional digital audio tape recorder (hereinafter referred to as DAT)
This enables high-density recording in applications such as

As an information converter using a modulation method, for example, THE
DAT CONFERENCE 5TANDA
There was one that used the 8-10 modulation system shown in RD (published June 1987).

The 8-10 modulation method is a PCM signal modulation method that divides information to be converted into 8-bit units and converts this into a 10-bit code.

However, since it is generally difficult to process low-frequency components in devices that record via a rotating transformer, it is desirable to use a DC-free modulation method with as small a low-frequency power spectrum component as possible.
is the detection window width, T, which represents the degree of margin that does not cause code errors when the time axis of the reproduced signal fluctuates due to jitter;
It is desirable that m1n (minimum magnetization reversal interval corresponding to the resolution of the recording mechanism) is large and that high-density recording is possible.

Further, it is desirable that Tmax/Tm1n be small in order to reduce peak shift due to code amount interference and improve override characteristics due to overwriting of signals, and it is desirable that Tm1n be large in order to reduce high frequency components as much as possible.

Note that Tmax is the maximum magnetization reversal interval.

FIG. 9 shows Tm1n, Tmax, Tmax/Tm1n,
Tw, TwXTmin, and DSVmax are shown. Note that DSV is Digital SumVaria
It is an abbreviation of tion, and it is defined as +1 [positive polarity] when the waveform after NRZI conversion of the modulation code string is high level, and -1 [negative polarity] when it is low level, and for each code [sign] of the modulation code string. Shows the integrated value. Also, CDS
(Codevord Dlgltal Sum) is
Refers to DSV within one of the above modulation codes (however, NRZ
I conversion starts from low level).

Generally, in digital recording, stochastic errors occur in the reproduced signal due to defects in the recording medium and system noise including tape noise.

For this reason, an error correction code is added and recorded for the purpose of decoding the reproduced signal to the original correct signal.

Note that in order to make the error correction code work effectively, the recording signal string is a group of information words (SYMBOL) containing an error correction code or an error detection code and a synchronization signal (SYMBOL).
BLOCK) is configured as shown in FIG. 1O, for example.

In FIG. 10, the synchronization signal is a signal for classifying information word groups, and is desired to be a highly reliable signal. Therefore, in DAT, a signal sequence (pattern)
00OI (X is 1 or O) is adopted.

FIG. 7 is a diagram showing the configuration of a modulation circuit using the 8-10 modulation method. In the figure, (1) indicates an 8-bit information word, a 1-bit table selection signal (Q'), and a 1-bit synchronization signal area. Codeword 10 with total lO bits of signal as input
The sum of the signals (Q) of bits and 1 bit that selects the table of the next codeword, the encoder outputting the bit, (2
) is the codeword table selection signal for one information word (SYMBO).
L) A flip-flop for delay.

Note that the relationship between the input information word and the output code word in the encoder (1) is that the CD5-0 code word has a one-to-one correspondence with the information word, and a table is used for other code words. Two codewords are prepared, and codewords with different CDSs are paired, and one information word is associated with two codewords.

Next, the operation will be explained.

When the synchronization signal area signal is input to the encoder (1) at High level and the table selection signal (Q') is input at +1, it does not depend on the information word (8 bits) and the output is as shown in Fig. 8. The code word 000010001 and +1 Q signal corresponding to 5YNC of the Q-1 table shown in FIG.

The +1 Q signal is then input to the flip-flop (2), delayed by one information word (SYMBOL), and input to the encoder (1) as a new table selection signal (Q').

Furthermore, a synchronization signal area signal is inputted at LOW level to the encoder (1), and a table selection signal (Q゛) is delayed by one information word (SYMBOL) in the flip-flop (2).
is input as +1 and the information word is FF, the output signal is 0,,01010 corresponding to FF of Q--1 shown in FIG.
The code word and the Q signal of -1 are output.

In addition, a 1 information word (SYMBOL) delay word encoder (1
), the synchronization signal area signal is input at a low level, and the flip-flop (2) inputs one information word (S
YMBOL) The delayed table selection signal (Q') is -
When the information recording is FF, the output signal is a code word of 101010 and a Q signal of -1, which corresponds to the FF of Q'-1 shown in FIG.

Thereafter, the 8-bit information word is converted into a 10-bit code word in the same manner.

[Problems to be Solved by the Invention] Since the conventional information converter is configured as described above, since Tm1n is as small as 0.8 digital clock period (T), code amount interference becomes large and TwXTmi n is 0
．． 64, which poses a problem even at high densities.Furthermore, the synchronization signal may have a pattern in which Tm1n and Tmax are adjacent to each other, and peak shifts due to code amount interference are likely to occur, resulting in poor reliability.

This invention was made to solve the above-mentioned problems, and aims to provide an information converter that is suitable for high-density recording without causing peak shifts due to code amount interference.

[Means for Solving the Problems] An information converter according to the present invention detects the least significant bit of a code word for previously converted m-bit information, and uses the information of the least significant bit and m bits to convert n A selection means for selecting the code of the bit and the value of the upper bit of the code, and a synchronization signal addition area signal when adding a synchronization signal, and a synchronization signal that meets the conditions of the encoding rule for information words and is continuous. and generating means for generating a synchronization signal pattern that cannot occur in the code string of the information word.

[Operation] When converting m-bit information into an n-bit code (m<n) by the selection means, the information converter according to the present invention selects any “1” in the converted code string and the next one. Appearing “1”
The least significant bit of the code word for the previously converted m-bit information is detected and the lowest Using the information of the lower bits and m bits, the code of n bits is selected and the value of the upper bits of the code is selected, and when the generation means adds the synchronization signal, the information word is A synchronization signal pattern that meets the conditions of the encoding rule and cannot occur in a code string of continuous information words is generated.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 is a block diagram showing the configuration of the information converter. In the figure, (3) is an input terminal (SYMBOL DATAIN) for information words in units of 8 bits, and (4) is connected to the input terminal (3). This is an encoder that converts an 8-bit information word input into a 14-bit code word shown in FIG. 5 based on the information of the A/100 group selection input terminal.
CDS corresponding to the code word output with the bit code word
The Q signal outputs information in 3 bits, and also indicates the state transition within the code word and indicates the polarity after NRZ 1 modulation of the converted code string (codes that end at High level are Q signal).
-1, and the code ending at the Low level is Q--1) is output as 1 bit, and further information words are output from 00 to 23.6F.
- In the case of AC or E5 to FF (all hexadecimal numbers), the signal for controlling the MSB of the code word to be converted (MSC output that is High when an information word is input, and Low otherwise) is 1 bit. It is designed to be output as .

(5) is a flip-flop connected to the output side of the encoder (4) and delays the LSB signal of the code word converted by the encoder (4) by one information word (SYMBOL);
) is connected to the output side of the encoder (4) and converts the MSB of the code word of the information word to 1 based on the MSC signal output from the encoder (4) and the output of the flip-flop (5). This is a gate that outputs 1 (a) under the condition that it is possible.

Furthermore, (7) is the output side of the encoder (4) and the gate (6)
A gate (8) is connected to the output side of the encoder (4) and converts the MSB of the code word output from the encoder (4) to 1 based on the output of the gate (6). 6
) is a polarity determiner which is connected to the output side of the codeword and outputs the polarity (b) after adding the Q signals of the past codewords by exclusive logical sum to determine the polarity after NRZI modulating the codeword string.

(9) is the output side of the encoder (4) and the gate (
6) and the output side of the polarity determiner (8) to output the polarity and gate (
It is an arithmetic unit that calculates the DSV of a code string based on the output of 6), and has a terminal (c) that outputs 1 only when DSV is 0, and a terminal (c) that outputs 1 when DSv is 0 and 10, and high when DSV is -. It has an output terminal (d).

Further, (10) is connected to the output side of the polarity determiner (8) and the output side of the arithmetic unit (9), and the DS
This is a gate that outputs the CDS conditions required for the code word in order to suppress the divergence of V, and is High when CDS>0.
It is designed to output Low when CDS<0.

Furthermore, (,) is connected to the output side of the gate (10) to suppress the divergence of the DSV among the two code words of group A or B prepared in the encoder (4) based on the output of the gate (10). A check circuit (1) outputting a group selection signal (GSEL) for selecting a code word of a group.
2) is a check pulse (CHKP) which is manually input to the check circuit (,) which checks whether the code word to be converted is selected from the group for suppressing DSV.

(13) is a gate for limiting code word selection to group A when DSV is 0 and the synchronization signal addition area, and (14) is connected to the output side of the encoder (4) as a synchronization signal. This is a gate for generating a pattern that does not occur in a code word string obtained by converting an information word.

Further, (15) is a parallel/serial converter connected to the output side of the encoder (4) and converts a 14-bit parallel signal into a serial signal by the encoder (4), and (16) is a parallel/serial converter. C0 output from (15)
DE OUT (code word string converted into serial).

Furthermore, (17) is a flip-flop (5) and an arithmetic unit (9).
), the Symbo I CLR, () input to the check circuit (,) and the parallel/serial converter (15).
1g) is Ch<nnel CLR manually input to the parallel/serial converter (15), (19) is the arithmetic unit (9)
and 5YNCAREA input to gate (13). Now, data word length mm3, code length n-14, Tm
If we construct a code such that ax / T min = 4, 0, then d (any ′, and the next “1
”) - 1, k (any “1”
The maximum number of "0"s between the next "1") is -7. However, the code uses the NRZI (F) rule.

To satisfy d-1, the MSB (most significant bit) of the code word must be set to "0°," and to satisfy -7,
The maximum number of consecutive “O”s in the code word.

When the MSB side is within 3 bits and the LSB (least significant bit) side is within 4 bits, the number of code words shown in FIG. 2 is obtained.

Here, in order to construct a DC-free code, 1,
It is sufficient that the same number of CDSs have the same absolute value.

Therefore, 85 of those whose CDS is -2, 85 of which are +2, 44 of which are -4, 44 of which are +4, 13 of which are -6, and 13 of which are +6.
, two with −8, and two with +8 are used as code words, and those with parentheses CDS≠0 are used as a pair of code words with CDS>0 and CDS<Q.

The code word thus obtained is divided into map I and map II, and these maps are switched and used so that the DSV decreases when forming one code sequence. however,
For CD5-0, the same code word is used for both map I and map (2).

When configured as above, the total codeword pairs are 1゜7+85
+44+13+2-251, resulting in 251 sets, which is 5 sets short of 8-bit data (256 pieces).

Therefore, a code that does not satisfy the above conditions, that is, a code in which the 4 bits on the MSB side are prefixed with "O#" is used.

Among these, for those that become CD5-0, MS
B- A code word that is “1” is used to form a pair, and when the LSB of the code word that was converted immediately before is “1”, a code word with the MSB side 4 bits prefixed with “0#” is used, and the LSB is “Oo”. Sometimes, a code word that is MSB-“1” is used.

Also, for CDS≠0, if the LSB of the code word converted immediately before is “0”, the MSB is set to “1”.
Convert to With this configuration, the number of code word pairs shown in FIG. 3 can be obtained.

By the way, among the codeword pairs shown in FIG. 3, CDS is ±
If we discard 2 sets of 8 and 9 of the sets of ±6, the total number of codeword pairs becomes 256, and a code is constructed.

Furthermore, of the above code word pair, the upper 2 bits of the MSB copper B side are 0.
For those with # and CD5-0, codewords whose MSB is 1# are used as a pair, and for pairs of codewords where CDS≠O and the upper 2 bits of the MSB copper B side are “Oo”, the codewords whose MSB is 1# are used as a pair. If the LSB of the converted code word is "0", the MSB is converted to "1". In this way, “1
'', that is, the number of magnetization reversals increases, and the low frequency component decreases.

The method for selecting the conversion code configured in this way is explained in the fourth section.
Code conversion tables are shown in FIGS. 5<a> to (h).

Note that the information conversion method according to this embodiment uses 8-bit 2
This converts the decimal data into 14-bit encoded data starting from the first bit of the converted encoded data.

With the above combination of conversion codes, the minimum value of the number of “0”s between any “1” and the next “1” in the converted encoded data is 1, and the maximum value is 7, that is. Tma
It becomes possible to realize encoding in which x/Tm1n=4.0.

Also, TwXTmin is 0.653, which is 8-10
It is larger than 0.64 of the modulation method, and high-density recording is possible. Moreover, the DSV divergence range is ±9 and is DC free.

Furthermore, when constructing a code word, the code string after conversion is...0100000001000000010001
0... ((7/8)X8T -4(7/8)x3T
→ (7/8)

Therefore, the synchronization signal does not occur in the code string of the above code word (7/8)X8T→(7/8)X8T→(7/8)X4
The T pattern is generated by the synchronization signal area signal.

Next, the operation of this embodiment will be explained.

Information word 60 (hexadecimal) is sent from the input terminal (3) to the encoder (4
), the MSC output of the encoder (4) is Low.
, and the code word of the information word that was just converted has an LSB of 1, and the output (a) of the gate (6) is Low (see FIG. 6).

Further, the output (b) of the polarity determiner (8) is Low,
The DSV value at the arithmetic unit (9) is O, and the output (C) is H.
igh, and the output (d) is Low.

As a result, priority is given to the code word of the information word 60 having a DSV of 0, and the information High of the output (c) of the arithmetic unit (9)
is applied to the A/100 group selection input terminal of the encoder (4) through the gate (13), and the encoder (4) outputs 010
A code word of 10101001010 is output.

At this time, CDS is outputted as -2, Q as -1, and MSC as Low.

In addition, in the case of DSV-0, although it is not related to the selection of code words A and B, the output of the gate (10) that outputs the CDS condition for suppressing the divergence of DSv has a low (negative) polarity, and the positive Or the negative condition output is Low (positive),
As a result, the selection condition is for the Low level (negative CD5) code.

Next, when the information word 61 is input, M of the encoder (4)
The SC output remains Low, and the output of the gate (6) (
a) also remains Low.

In addition, the output (b) of the polarity determiner (8) is the level Low up to just before the information word 60 and the Q output of the information word 60 -1 (Lo
w) It is also a Low level due to the exclusive OR of the levels.

Furthermore, the arithmetic unit (9) calculates the DSV immediately before the information word 60.
−0, and the code word selected in this way is Symbo.
At the rising edge of I CLR (17), it is loaded to parallel/serial converter rA (15), and Ch<nne l
One bit is serially output every time CLR (18) rises.

Then, at the rising edge of the Symbo I CLR (17), the CDS and Q signals output from the encoder (4) are converted to the previous DSV by the arithmetic unit (9).
The Q signal is exclusive-ORed with the previous polarity in the polarity determining circuit (8). That is, C of information word 60
D5--2 is added to become DSV--2, and the arithmetic unit (
The output (C) of 9) becomes Low and the output (d) becomes Hi.
It becomes gh.

As a result, the output of the gate (10) becomes High level, and the code word condition of CDS>0 is output, and as a result, GSEL, which is output to the check circuit (,), first becomes the gate (10).
10) is output as it is at H1gh level, and the A/T3 terminal of encoder (4) goes to H1gh level through gate (13).
The code word of group A of the information word 61 is output from the encoder (4). At this time, CDS is -2, Q
is -1, and MSC is outputted as Low.

Next, the check pulse (CHKP) is activated by the check circuit (,
), the DS is calculated based on the CDS of the currently selected code word and the output of the gate (10).
A check circuit (,) determines whether a code word in the direction of suppressing V is selected.

The CDS of the selected codeword is −2, and the gate (
In the output of 10), the condition of CDS>0 is input, and the selected code word is determined to be NG. Then, the check circuit (,) connects the gate (10) to the output EXOR gate at the rising timing of the check pulse (CHKP).
) is connected to the terminal that is different from the one to which the output is connected.
As a result, GSEL is inverted from High to Low level.

As a result, the A/Hyakujin power terminal of the encoder (4) becomes Low, the encoder (4) outputs the code word 01001010010100 (1294) of the B group of the information word 61, and the CDS, Q, and MSC signals are also +4 each. ．． L Low
is output. Similarly to the above, the results are converted to Symbo I
The code word is added to the parallel/serial converter (15) by the CLR (17), LOADL and CDS are added by the arithmetic unit (9), and Q is exclusive ORed by the polarity determination circuit (8).

Next, when 7A is input manually following the information word 61, the gate (
In the output (a) of 6), the LSB of the immediately preceding code word is 0, the MSC of the information word 7A is High, and as a result, the code word for the information word is High regardless of the A group/B group, and the MSB is the gate ( 7) is converted to 1. Accordingly, the CDS corresponding to the code word is processed as the one output from the encoder (4) multiplied by -l.

Also, since the Q signal also increases by one inversion, the encoder (4)
It is processed by multiplying the output by -1 (exclusive OR of the output of the gate (6) and the output of the encoder (4)).

As a result, the output of the gate (10) is at the HLgh level, and the output of the check circuit (,) is GSE.
L is also High and the encoder (
The A/B terminal of 4) is also High, and the encoder (4)
) is selected from group A of information word 7A, and is 00001000000010 (0202
). At this time, CDS is +2, Q signal is -1, MS
C is output as High.

Next, the check pulse (CHKP) is activated by the check circuit (,
), the DS is calculated based on the CDS of the currently selected code word and the output of the gate (10).
A check circuit (,) determines whether a code word in the direction of suppressing V is selected.

Since the MSB of the code word is converted to 1 as described above, the CDS of the selected code word is the CDS output from the encoder (4) multiplied by -1, resulting in CD5--2. Further, the output of the gate (10) is High,
Since CDS>Q, the selected code word is determined to be NG, and the check circuit (,) outputs a check pulse (
Output EXOR at the rising edge of CHKP)
A terminal different from the terminal to which the output of the gate (10) is connected to the gate is set to High level, and as a result, GSEL is inverted and is inverted from High to Low level.

As a result, the A/hyakujin power terminal of the encoder (4) becomes Low, the encoder (4) outputs the code word 00001001001010 (024A) of the B group of the information word 7A, and the CDS, Q, and MSC signals are also - 4,-1,Hi
gh is output.

As before, the results were converted to Symbol CLR (17
The code word from the encoder (4) whose MSB has been converted to 1 by 9) and the Q obtained by multiplying the Q from the encoder (4) by -1 is subjected to exclusive OR in the polarity determining circuit (8).

Next, when an area for adding 2 SYMBOL synchronization signals following information word 7A is input, 5YNCAREA (1
9) The signal is set to High only for 2 SYMBOL of the synchronization signal addition area.

As a result, the operations of the polarity determiner (8), the arithmetic unit (9), and the check circuit (,) are stopped when the synchronization signal is added. That is, when a synchronization signal is added, the function for realizing DC-free is temporarily stopped and held until the normal information word that follows the synchronization signal is converted. To do this, the synchronization signal should be CD5-0, Q-1 within 2SYMBOL (28 channel bits), and this allows the synchronization signal to be applied to the converted data of the information words on both sides of the synchronization signal area. Patterns have no effect.

Next, the operation of generating a synchronization signal pattern will be explained.

First, in the synchronization signal area for 2 SYMBOLs, the SYMBOLDATA IN input to the encoder (4)
For the information in (3), two information words with 89 at the front and 62 at the rear are assigned.

At this time, A/100 of the encoder (4) is High because 5YNCAREA (19) via the gate (13) is High.
Fixed at gh level.

As a result, all code words output from the encoder (4) are selected from group A, and are 00100001000.
001.01001000010000 is output.

Further, the MSC is Low, and the MSB of any of the above code words is never converted to 1. Note that the CDS and Q signals are ignored in the synchronization area.

Next, since 5YNCAREA (19) is High in the above two code words, the sign of the LSB and the 10th 2 bits are inverted by the gate (14). As a result, the code word input to the parallel/serial converter (15) is 00101001000000,1
It becomes 000000010001.

Then, the code word re-encoded by the gate (14) is sent to the output of C0DE OUT (16) as NR2! The modulated one is CD5-0.0--1, and the synchronization signal is (7/8)X8T→(7/8)X8T→(7/8).
8) An X4T pattern is obtained.

Note that this pattern has a 0-run length obtained by the information converter that is limited to a range of 1 to 7, and is a unique pattern that does not occur in consecutive patterns.

Next, when OO is input as a normal information word following the synchronization signal area, the A/s input of the encoder (4) is given the output of the gate (10) immediately before the synchronization signal area, and the CD
It is High with S>0. As a result, group A is selected as the code word and 00001000000100
(0204) is output, and CD5-0. Q--1
, MSC-High is one conversion of the MSB of the code word, the LSB of the synchronization signal is 1, and the gate (6) is closed.

It is not done to get a W.

Next, the check pulse (CHKP) is activated by the check circuit (,
), the DS is calculated based on the CDS of the currently selected code word and the output of the gate (10).
A check circuit (,) determines whether a code word in the direction of suppressing V is selected.

The CDS of the selected codeword is 0, and 0 is +, -
It is set to be judged as 10 at the time of judgment, and the gate (
The output of lO) matches CDS>0 (High), and the selected code word is determined to be OK. As a result, the EXOR gate of the output of the check circuit (,) is connected to the gate (1
The terminal other than the one to which the output of 0) is connected remains at Low level, and GSEL remains at H1g.
h level is output.

As a result, the A/r3 input terminal of the encoder (4) becomes High.
h, and the code words of group A continue to be output, and the CDS, Q, and MSC are also 0. -1. High
It remains h.

In the above-mentioned embodiment, CD5-0 is set to 10, but it is not limited to this, and it may be set to -, and CD5-0
In this case, both groups A and B have the same code and no problem occurs.

Furthermore, in the above embodiment, the synchronization signal pattern is generated by re-encoding the information word 89.62 using the gate (14), but the present invention is not limited to this, and the pattern of the synchronization signal area becomes CD5-O. Q-1, and the pattern may include a means for realizing a pattern in which the θ run length is 7-47-3, which corresponds to the gate (14).

[Effects of the Invention] As explained above, according to the present invention, when m-bit information is converted into an n-bit code, any “1” in the converted code string and the next “1#” are The least significant bit of the code word for the previously converted m-bit information is detected and the lowest Since the configuration uses the information of the lower bits and m bits to select the n-bit code and the value of the upper bits of the code, Tm1n and Tmi are DC-free.
nXTw allows higher density than conventional 8-10 modulation. Further, since the synchronization signal pattern is not generated in a pattern sequence obtained by re-encoding the code word and encoding normal information, a peak shift does not occur and high reliability can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an information converter according to an embodiment of the invention, FIG. 2 is a diagram showing the number of code words, and FIG.
Figure 4 shows the number of codeword pairs, Figure 4 shows the conversion code selection method, Figure 5 shows the code conversion table, and Figure 6 shows the code conversion table.
7 is a diagram showing the configuration of a conventional 8-10 modulation circuit, FIG. 8 is a timing chart diagram showing a conventional data conversion example, and FIG. 9 is a diagram showing a performance parameter comparison table. FIG. 10 is a diagram showing a case example of an information string. In the figure, (4) is a selection means, and (14) is a generation means. Note that the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] In an information converter in which m-bit information words are divided and transmitted in units of one word (an integer of 1>2) including a synchronization signal, the least significant bit of the code word for the previously converted m-bit information is detected. A selection means that selects the n-bit code and the value of the upper bit of the code using the information of the least significant bit and the m bit; generation means for generating a synchronization signal pattern that meets the conditions of the encoding rule and that cannot occur in a code string of continuous information words, the selection means converts m bits of information into n bits. When converting to a code (m<n), there are at least 1 and no more than 7 “0” between any “1” in the converted code string and the next “1”, and In order to keep the DSV divergence range within ±9, the least significant bit of the code word for the previously converted m-bit information is detected and the least significant bit and m
An information converter characterized in that the n-bit code is selected using bit information and the value of the upper bit of the code is selected.