JPH0344232A - Monitor circuit for hdlc line - Google Patents

Abstract

PURPOSE:To detect a control pattern of a transmission data signal or a reception data signal passing through an HDLC line in the operating state with a simple circuit by providing a flag pattern detection circuit, a control pattern detection circuit and a display circuit. CONSTITUTION:A flag pattern detection circuit(FLGDTC) 1 receives a transmission data signal or a reception data signal and a clock signal to detect a flag pattern of the data signal and outputs a frame signal consecutive to the flag pattern. A control pattern detection circuit(CTLDTC) 2 receives a frame signal outputted from the FLGDTC1, eliminates an address pattern included in the frame signal and detects only the control pattern. An LED display circuit 3 receives the control pattern outputted from the CTLDTC2, operates one of plural LED display devices to display the type of the pattern. Thus, the control pattern of the transmission data signal or the reception data signal passing timewise through the HDLC line is detected with a simple circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an HDLC line monitor circuit, and in particular, to a monitor circuit for an HDLC line, which is connected to a connection point between a data terminal device and a data line termination device to control a transmitted data signal or a received data signal. The present invention relates to a H1) LC line monitor circuit that visually displays the type of pattern.

[Conventional technology]

A conventional HDLC line monitor circuit is provided as a dedicated measuring device that can not only know the type of control pattern of a transmitted data signal or a received data signal, but also monitor everything from the leading flag pattern to the contents of successive frame signals. I was using what I had.

[Problem to be solved by the invention]

The conventional HDLC line monitor circuit described above takes the form of a dedicated measuring device, so its shape and size do not take into account installation within a data communication device. There is a problem in that it cannot be easily measured and each of the five measurements itself is expensive.

An object of the present invention is to provide an HDL that makes it possible to know, with a simple circuit, the control pattern of a transmitted data signal or a received data signal that passes through all HDLC lines during operation.
The purpose of this invention is to provide a C line monitor circuit.

[Means to solve the problem]

The HDLC line monitor circuit of the present invention is connected to a connection point between a data terminal device and a data line termination device of an HDLC line, and receives a transmission data signal or a reception data signal and a clock signal defined at the connection point. a flag pattern detection circuit that detects a flag pattern of the transmitted data signal or the received data signal and outputs a frame signal cascading to the flag pattern; and a flag pattern detection circuit that receives a frame signal output from the flag pattern detection circuit and includes the frame signal in the frame signal. a control pattern detection circuit that detects and outputs only the control pattern by removing the address pattern that is generated; and a plurality of indicators that receive the control pattern output from the control pattern detection circuit and are provided corresponding to the type of the control pattern. This configuration includes a display circuit that operates one of the display circuits to display the type of pattern.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Flag pattern detection circuit (hereinafter referred to as FLGDTC) 1
is a control pattern of the 0th stage that receives a transmitted data signal or a received data signal (hereinafter referred to as a data signal) and a clock signal, detects a flag pattern of the data signal, and outputs a frame signal cascaded to this flag pattern. The detection circuit (hereinafter referred to as CTLDTC) 2 is FLGDTCI
It receives the frame signal output by the frame signal, removes the address pattern contained in this frame signal, and detects only the control pattern. LED display circuit (hereinafter referred to as LEDDSP) 3
receives the control pattern output from CTLDTC2 and displays a plurality of LEDs corresponding to the type of this control pattern.
Operate one of the indicators to display the type of pattern.

Next, the operation of this embodiment will be explained.

FIG. 2 is a block diagram of the flag pattern detection circuit (FLGDTC).

FLGDTC1 transmits the data signal and the clock signal to the fifth
As shown in the data signal and clock signal relationship diagram in the figure, the data column signal is detected at the rising edge of the clock and recognized as a serial data bit. The abort pattern detection circuit 4, which first receives a data signal and a clock signal, detects whether the arrangement of the serial data bits described above is all "1" or not, and when detecting a data bit that is not "1", the next A non-abort state detection signal is sent to the flag pattern detection circuit 5 of the stage. Upon receiving the non-abort state detection signal, the flag pattern detection circuit 5 monitors the arrangement of a series of serial data bits and detects a flag pattern. When flag pattern detection circuit 5 detects a flag pattern, it sends a flag pattern detection signal to frame detection circuit 6 at the next stage. Frame detection circuit 6
extracts the frame signal from the data signal and converts it to CTLDTC
Send to 2. FIG. 6(a) shows a state in which a frame signal is extracted from the data signal.

FIG. 3 is a block diagram of the control pattern detection circuit (CTLDTC).

The frame signal received from FLGDTCI is input to the address pattern detection circuit 7 at the same time as the clock signal. Address pattern detection circuit 7 detects an address pattern in the frame signal shown in FIG. 6(b), and sends an address pattern detection signal to control pattern detection circuit 8 at the next stage. The control pattern detection circuit 8 that has received the address pattern detection signal, as shown in FIG. 6(b),
Control pattern is cut out from the frame signal and LEDDS
Send to P3.

FIG. 4 is a block diagram of the LED display circuit (LEDDSP).

The serial-to-parallel converter circuit 9 that has received the control pattern from the CTLDTC 2 uses the first 8 bits of the control pattern as a control field signal to be sent to the control pattern classification circuit in the next stage, as shown in FIG. 6(C). Output in parallel to 0. The control pattern classification circuit 10 that has received the control field signal knows whether the first bit of the control field signal is "0" or "1", and determines that it is an I frame if r□. Next, the first bit of the control field signal is 1
1”, the second bit is “O” or “1”.
”, and if “OJ”, it is determined that it is an S frame, and if it is “1”, it is determined that it is a U frame.0
Next, the above-mentioned results are output as an E-frame detection signal, an S-frame detection signal, or a U-frame detection signal so that the LED corresponding to each detection signal is displayed. c) shows the case of ■ frame.

〔Effect of the invention〕

As explained above, the present invention enables HDLC during operation.
This has the effect that it is possible to know the control pattern of the transmitted data signal or received data signal that passes over the line moment by moment with a simple circuit.

[Brief explanation of drawings]

Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 is a block diagram of a flag pattern detection circuit (FLGDTC), Figure 3 is a block diagram of a control pattern detection circuit (CTLJ), and Figure 4 is a block diagram of a control pattern detection circuit (CTLJ). A block diagram of the LED display circuit (LED DSP), Figure 5 is a data signal and clock signal relationship diagram,
FIG. 6 is an explanatory diagram of a data signal extraction situation. 1...Flag pattern detection circuit (FLGDTC)
), 2... Control pattern detection circuit (CTLDT
C>, 3...LED display circuit (LEDDSP)
, 4...Abort pattern detection circuit, 5...
... Flag pattern detection circuit, 6 ... Frame detection circuit, 7 ... Address pattern detection circuit, 8 ... Control pattern detection circuit, 9 ......
・Serial-to-parallel conversion circuit, O... Control pattern classification circuit.

Claims (1)

[Claims] Connects to a connection point between a data terminal device and a data line termination device of an HDLC line to receive a transmission data signal or reception data signal and a clock signal defined at the connection point, and transmits the transmission data signal or reception data signal. a flag pattern detection circuit that detects a flag pattern and outputs a frame signal cascading to the flag pattern; and a flag pattern detection circuit that receives the frame signal output from the flag pattern detection circuit, removes the address pattern included in the frame signal, and outputs only the control pattern. a control pattern detection circuit that detects and outputs the control pattern; and a control pattern detection circuit that receives the control pattern output from the control pattern detection circuit and operates one of a plurality of indicators provided corresponding to the type of the control pattern to indicate the type of pattern. HDLC characterized by having a display circuit for displaying
Line monitor circuit.