JPH0344356U

JPH0344356U -

Info

Publication number: JPH0344356U
Application number: JP10270789U
Authority: JP
Priority date: 1989-09-01
Filing date: 1989-09-01
Publication date: 1991-04-24

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例による多重通信シ
ステムの概略ブロツク図、第２図は第１図のアド
レス線およびデータ線の波形図、第３図はこの考
案の一実施例による基準信号発生用発振回路の詳
細回路図、第４図は送受信回路の回路図、第５図
は基準信号発生用発振回路のタイミングチヤート
、第６図乃至第８図は送受信回路のタイミングチ
ヤート、第９図は従来の時分割制御バス装置の実
施態様を示す概略図である。図において、１……基準信号発生用発振回路、
２−１〜２−３，２−（ｎ−２）〜２−ｎ……送
受信回路、３……アドレス線、４……データ線、
２０−１〜２０−３，２０−（ｎ−２）〜２０−
ｎ……外部装置。なお、図中、同一符号は同一、
又は相当部分を示す。 Fig. 1 is a schematic block diagram of a multiplex communication system according to an embodiment of this invention, Fig. 2 is a waveform diagram of the address line and data line of Fig. 1, and Fig. 3 is a reference signal generation according to an embodiment of this invention. 4 is a circuit diagram of the transmitting/receiving circuit, FIG. 5 is a timing chart of the reference signal generating oscillating circuit, FIGS. 6 to 8 are timing charts of the transmitting/receiving circuit, and FIG. 9 is a detailed circuit diagram of the transmitting/receiving circuit. 1 is a schematic diagram illustrating an embodiment of a conventional time-sharing control bus device; FIG. In the figure, 1... an oscillation circuit for generating a reference signal;
2-1 to 2-3, 2-(n-2) to 2-n...transmission/reception circuit, 3...address line, 4...data line,
20-1 to 20-3, 20-(n-2) to 20-
n...External device. In addition, in the figure, the same reference numerals are the same,
or a corresponding portion.

Claims

[Scope of utility model registration request]

An oscillation circuit 1 for generating a reference signal, and a plurality of transmitting/receiving circuits 2-1 to 2-1, each having a unique number of addresses.
2-n, this oscillation circuit 1, and each transmitting/receiving circuit 2-1
-2-n, and a data line 4 that connects each transmitting/receiving circuit 2-1 to 2-n. Multiplex communication configured to count reference signals and enable communication between external devices 20-1 to 20-n connected to each of the transmitting/receiving circuits 2-1 to 2-n whose value matches the number of set addresses. system.