JPH0344737U - - Google Patents
Info
- Publication number
- JPH0344737U JPH0344737U JP10627689U JP10627689U JPH0344737U JP H0344737 U JPH0344737 U JP H0344737U JP 10627689 U JP10627689 U JP 10627689U JP 10627689 U JP10627689 U JP 10627689U JP H0344737 U JPH0344737 U JP H0344737U
- Authority
- JP
- Japan
- Prior art keywords
- processor
- memory
- written
- specific area
- redundant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Description
第１図は本考案の一実施例を示す構成ブロツク
図、第２図は従来の冗長化プロセツサ装置の構成
概念図である。
ＰＣ１，ＰＣ２……プロセツサ装置、ＢＳ１…
…二重化バス、ＢＳ２……Ｉ／Ｏバス、１１……
メモリ、１２……特定領域、１３……演算制御部
、１４……メモリアクセス手段、１５，１６……
バスドライバ。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a conceptual diagram of a conventional redundant processor device. PC1, PC2...processor device, BS1...
...duplex bus, BS2...I/O bus, 11...
Memory, 12...Specific area, 13...Arithmetic control section, 14...Memory access means, 15, 16...
bus driver.
Claims (1)
セサ装置を用意し、一方のプロセツサを実作業に
つかせ、他方のプロセツサは一方のプロセツサの
異常に備えて待機状態になるように構成された装
置において、 前記２つのプロセツサ装置のそれぞれに、自身
のメモリの特定領域にデータを書き込むと前記二
重化バスを介して他方のプロセツサ装置内のメモ
リの特定領域に同一のデータを書き込むことがで
きるように構成したメモリアクセス手段を設けた
ことを特徴とする冗長化プロセツサ装置。[Claim for Utility Model Registration] Two processor devices connected via a redundant bus are prepared, one processor is used for actual work, and the other processor is placed on standby in case of abnormality in one processor. In an apparatus configured such that, when data is written to a specific area of its own memory in each of the two processor units, the same data is written to a specific area of the memory of the other processor unit via the duplex bus. 1. A redundant processor device comprising memory access means configured to allow writing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10627689U JPH0344737U (en) | 1989-09-11 | 1989-09-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10627689U JPH0344737U (en) | 1989-09-11 | 1989-09-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0344737U true JPH0344737U (en) | 1991-04-25 |
Family
ID=31655012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10627689U Pending JPH0344737U (en) | 1989-09-11 | 1989-09-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0344737U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006268596A (en) * | 2005-03-25 | 2006-10-05 | Fujitsu Ltd | Service system redundancy method |
-
1989
- 1989-09-11 JP JP10627689U patent/JPH0344737U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006268596A (en) * | 2005-03-25 | 2006-10-05 | Fujitsu Ltd | Service system redundancy method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0344737U (en) | ||
| JPS6392963U (en) | ||
| JPS63199342U (en) | ||
| JPS61128739U (en) | ||
| JPS6380603U (en) | ||
| JPH0289508U (en) | ||
| JPH0258845U (en) | ||
| JPH0263115U (en) | ||
| JPS63163543U (en) | ||
| JPS5876937U (en) | Input device for electronic equipment | |
| JPH0436647U (en) | ||
| JPH0235217U (en) | ||
| JPS6151548U (en) | ||
| JPH02143601U (en) | ||
| JPS6130148U (en) | Multiprocessor with shared memory | |
| JPH0223754U (en) | ||
| JPS6435439U (en) | ||
| JPS6361046U (en) | ||
| JPH0218155U (en) | ||
| JPS58171503U (en) | numerical control device | |
| JPH0280855U (en) | ||
| JPH021754U (en) | ||
| JPS5832543U (en) | shared storage | |
| JPS62151660U (en) | ||
| JPH03119236U (en) |