JPH0345045A - Signal input and output interface circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a signal input/output interface circuit that transmits and receives electrical signals at high speed between or within integrated circuits in integrated ultra-high-speed optical repeaters, etc. due to stray capacitance. In order to reduce the effects of characteristic deterioration, we have developed a current drive circuit that sends a current according to a human input signal to one end of the transmission line, and a gate terminal that is grounded and a source terminal that is connected to the other end of the transmission line. a field effect transistor;
The current source is connected to either the sending side of the current drive circuit or the source terminal of the field effect transistor and provides a bias current.

[Industrial application field]

The present invention relates to a signal input/output interface circuit for exchanging electrical signals between or within integrated circuits at high speed in an integrated ultrahigh-speed optical repeater or the like.

[Conventional technology]

Signal interfaces between high-speed circuits become more susceptible to stray capacitance as signals become faster. For example, an optical repeater converts an input optical signal into an electrical signal and then converts it back into an optical signal to relay the signal, but in ultra-high-speed optical repeaters with a bit rate of 10 Gbps or higher, the signal is handled internally. The influence of stray capacitance on electrical signals can no longer be ignored.

FIGS. 6 and 7 show the configuration of a conventional example for transmitting and receiving electrical signals.

FIG. 6(a) shows the configuration when oven sauce is used on the transmitting side. The transmitting side is a field effect transistor (FET)
) 611 as an output terminal, and the signal to be transmitted is input to the gate terminal of FET 611. On the receiving side, a terminating resistor 631 is connected to the input terminal, and a signal input to this input terminal is received by the gate terminal of the FET 621.

Further, FIG. 7(a) shows a configuration in which the transmitting side is an oven drain. On the transmitting side, the drain terminal of FET 711 is used as an output terminal, and a signal to be transmitted is input to the gate terminal of FET 711. On the receiving side, a terminating resistor 731 is connected to the input terminal, and the signal input to this input terminal is F
The receiver is taken at the gate terminal of ET721.

[Problem to be solved by the invention]

By the way, in the above-mentioned conventional system, there was a problem in that the characteristics deteriorated because the stray capacitance of the transmission line was added in parallel to the terminal resistor on the receiving side.

When the sending side is oven sauce, Fig. 6 (a)
As shown in FIG. 2, a stray capacitance 641 is added in parallel to the terminating resistor 631, and the terminating resistor 631 and stray capacitance 641 determine the cutoff wave number of the interface section. Therefore, as shown in FIG. 2(b), the gain on the transmitting side deteriorates in the high frequency region.

Similarly, when the sending side is an oven drain,
As shown in FIG. 7(a), a stray capacitance 741 is added in parallel to the terminating resistor 731, and as shown in FIG. 7(b), the gain on the transmitting side in a high frequency region is degraded.

The present invention was created in view of these points, and an object of the present invention is to provide a signal input/output interface circuit in which the influence of characteristic deterioration due to stray capacitance is reduced.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of a signal input/output interface circuit according to the present invention.

In the figure, a current drive circuit 111 sends a current according to an input signal to one end of a transmission line.

The field effect transistor 121 has a gate terminal grounded and a source terminal connected to the other end of the transmission line.

The current source 131 is connected to either the sending side of the current drive circuit 111 or the source terminal of the field effect transistor 121, and provides a bias current.

Therefore, the current according to the human input signal is sent to the transmission line by the current drive circuit 111, and the field effect transistor 121
The device is configured to send and receive signals by picking up the receiver at the source terminal of the device.

[For production]

By driving the current drive circuit 111, a current according to the human input signal is sent to the transmission line, and is supplied to the source terminal of the field effect transistor 121 whose gate is grounded. Further, a current source 131 is connected to either the sending side of the current drive circuit 111 or the source terminal of the field effect transistor 121, and a bias current is added to the transmitted current.

In the present invention, the current drive circuit 111 operating as a current source transmits a signal and receives the signal from the source terminal side of the field effect transistor 121, thereby reducing the input impedance on the receiving side.

In addition, a current source 1 is connected to either the sending side of the current drive circuit 111 or the source terminal of the field effect transistor 121.
By connecting 31, a predetermined bias current is added to the transmitted signal, and a large current amplitude is eliminated, so that the degree of fluctuation in the potential of the source terminal of the field effect transistor 121 is reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of the signal input/output interface circuit in the first embodiment of the present invention. In the figure, 211,2
21 and 231 indicate FETs, 213° and 223.233 a resistor, 225 a battery, and 241 the stray capacitance of the transmission line.

The "transmitting side" and the "receiving side" correspond to each of two integrated circuits that send and receive signals, or to the sending and receiving sides of a signal within one integrated circuit.

On the signal transmission side, the source terminal of the FET 211 is connected to the power supply terminal VSS via a resistor 213,
The drain terminal is connected to one end of the transmission line. A signal sent to the transmission line is input to the gate terminal of FET 211.

On the signal receiving side, the source terminal of FET221 is F
It is connected to the drain terminal of ET231 and the other end of the transmission line described above. The gate terminal of FET221 is connected to battery 2.
25, and the drain terminal is connected to resistor 2.
Power terminal ■ through 23. ,It is connected to the. Also,
The gate terminal of the FET 231 is connected to the power supply terminal V3S, and the source terminal is connected to the power supply terminal V3S through the resistor 233.
5. It is connected to the.

The FET 211 and resistor 213 on the transmission side operate as a current drive circuit that sends out an input signal in response to changes in current. When an input signal is input to the gate terminal of the FET 211, a gate-source voltage VGS is determined according to this input signal, and a drain current corresponding to this voltage VCS is sent to the transmission line.

FET 231 and resistor 233 on the receiving side are FE
It operates as a current source that supplies bias current to T221, and the sum of this bias current and the current supplied via the transmission line becomes the drain current of FET221. Therefore, since a change in the current supplied via the transmission line appears as a change in the drain current of the FET 221, by extracting this change in drain current as a voltage drop across the resistor 223, the transmitted signal can be received. will be held.

Further, a predetermined potential (fixed value) is supplied from the battery 225 to the gate terminal of -FET 221, and the potential of the source terminal varies depending on the drain current. By the way, this drain current is the sum of the predetermined bias current and the current received through the transmission line, so the change in the overall drain current is smaller than the degree of change in the current supplied through the transmission line. The degree becomes smaller. Moreover, this drain current (■.) and gate-source voltage ■. What is I?

=K (Vcs-V)2 (where K, V, and h are constants), and the degree of change in gate-source voltage VGS corresponding to change in drain current becomes small.

In the above-described configuration, since the input impedance on the receiving side is small, the switching frequency of the receiving side input section is high, and even if stray capacitance is added, deterioration of frequency characteristics can be suppressed.

In addition, by reducing the degree of change in the gate-source voltage (6) of the FET 221, the stray capacitance of the transmission line can be charged and discharged, so the rise time and fall time of the signal waveform are improved. The influence of characteristic deterioration due to stray capacitance can be reduced.

FIG. 3 shows the configuration of the second embodiment. The second embodiment has a configuration in which the FET 231 and resistor 233 on the receiving side of the first embodiment described above are replaced with FET 331 and resistor 333 on the transmitting side, and the other configurations are the same as those in the first embodiment. Same as .

As in the first embodiment, since the human power impedance on the receiving side is small, deterioration of frequency characteristics due to stray capacitance can be prevented by tr.
can be increased. Further, the drain current of FET211 is the same as that of FET331. It is added to the bias current generated by the current source constituted by the resistor 333 and sent to the transmission line. Since the current passing through this transmission line becomes the drain current of the FET 221, fluctuations in the potential of the source terminal of the FET 221 are suppressed, and the influence of characteristic deterioration due to stray capacitance can be reduced.

FIG. 4 shows the configuration of the third embodiment.

In the figure, 411, 413, 415, 421° 425
．． 431,435 is FET, 417,423.427
, 433, 437 are resistors, 429 are batteries, 441
, 442 indicate the floating resistance of the transmission line, respectively.

On the transmitting side, FET4 L1, 413 constitutes a differential pair, and in combination with a current source constituted by FET 415 and resistor 417, a current drive circuit is constituted. Signals whose logics are inverted are input to each gate terminal of the FETs 411 and 413, and currents corresponding to these inputs are sent to the two transmission lines.

The FETs 421 and 425 on the receiving side are for receiving and taking the current manually applied via these two transmission lines. The source terminal of FET 421 is connected to FET 431. which operates as a current source. A bias current is supplied by the resistor 433, and a bias current is supplied by the FET 435 operating as a current source and the resistor 437 to the source terminal of the FET 425.

Therefore, as in the first embodiment, the input impedance on the receiving side is small, the deterioration of frequency characteristics due to stray capacitance is small, and fluctuations in the potential of each source terminal of FET 421 and 425 are suppressed, and the two transmission lines It is possible to reduce the influence of deterioration in the rise and fall times of the output waveform due to each stray capacitance.

FIG. 5 shows the configuration of the fourth embodiment. The fourth embodiment uses FET431.435 on the receiving side of the third embodiment described above.
．． Resistors 433 and 437 are connected to transmitter FETs 531 and 5.
35. It has a configuration in which resistors 533 and 537 are replaced, and other configurations are the same as in the third embodiment.

The drain current of FET411 or FET413 is
FET531. The bias current generated by the current source composed of resistor 533 or the bias current generated by the current source composed of FET 535 and resistor 537 is added to 2.
are sent out to each of the two transmission lines. Since the current passing through each of these transmission lines becomes the drain current of FET 22 or FET 425, the FET
Fluctuations in the potential of each of the source terminals 421 and 425 are suppressed, and since the human input impedance is also small, the influence of characteristic deterioration due to stray capacitance can be reduced.

〔Effect of the invention〕

As described above, according to the present invention, a current corresponding to a signal sent out by a current drive circuit operating as a current source is received and taken by the source terminal of a field effect transistor whose gate is grounded, and this source terminal or By connecting a current source that provides a bias current to one of the sending sides of the current drive circuit, it is possible to reduce the input impedance on the receiving side and suppress fluctuations in the potential of the source terminal of the field effect transistor on the receiving side. can. Therefore,
This is extremely useful in practice because it can reduce the influence of characteristic deterioration due to stray capacitance of the transmission line.

[Brief explanation of drawings]

Figure 1 is a principle diagram of the signal input/output interface circuit of the present invention, Figure 2 is a configuration diagram of the first embodiment, Figure 3 is a configuration diagram of the second embodiment, and Figure 4 is the configuration of the third embodiment. 5 is a configuration diagram of the fourth embodiment, FIG. 6 is an explanatory diagram of the conventional example, and FIG. 7 is an explanatory diagram of the conventional example. In the figure, 111 is a current drive circuit, 121 is a field effect transistor, 131 is a current source, 211, 221. 231, 331. 411. 4
13. 415. 421. 425. 431. 4
35°531.535 is a field effect transistor (FET)
), 213.223,233,333,417,423
．． 427, 433, 437, 533, 537 are resistors, 225.429 are batteries, and 241.441, 442 are stray capacitances. <only/b) Usage εhe) da (Q age Muβ month ri Figure 6 (b)

Claims (1)

[Claims] (1) A current drive circuit (111) that sends a current according to an input signal to one end of the transmission line, and a field effect transistor (121) whose gate terminal is grounded and whose source terminal is connected to the other end of the transmission line. ), and a current source (131) connected to either the sending side of the current drive circuit (111) or the source terminal of the field effect transistor (121) and providing a bias current. A signal input/output interface circuit featuring: