JPH034546A - Semiconductor mounting device - Google Patents
Semiconductor mounting deviceInfo
- Publication number
- JPH034546A JPH034546A JP1140476A JP14047689A JPH034546A JP H034546 A JPH034546 A JP H034546A JP 1140476 A JP1140476 A JP 1140476A JP 14047689 A JP14047689 A JP 14047689A JP H034546 A JPH034546 A JP H034546A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor element
- board
- pressed
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07141—Means for applying energy, e.g. ovens or lasers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07173—Means for moving chips, wafers or other parts, e.g. conveyor belts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
- H10W72/07338—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
Landscapes
- Electronic Switches (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は各種電子機器に利用される半導体の実装装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor mounting device used in various electronic devices.
従来の技術
従来の技術を第2図(IL) (b)とともに説明する
。Prior Art The conventional technology will be explained with reference to FIG. 2 (IL) (b).
まず第2図(&)に示すようにセラミック、ガラス。First, as shown in Figure 2 (&), ceramic and glass.
ガラスエポキシ等よシなる配線基板1の導体配線2を有
する面に絶縁性の樹脂5を塗布する。導体配線2はcr
−ムU、ム(1、au 、 ito等であり、樹脂6は
熱硬化型又は紫外、庫硬化型のエポキシ。An insulating resin 5 is applied to the surface of a wiring board 1 made of glass epoxy or the like having conductor wiring 2. Conductor wiring 2 is cr
-mu U, mu (1, au, ito, etc.), and the resin 6 is a thermosetting type or an ultraviolet or warehouse curing type epoxy.
シリコン、アクリル等である。次に第2図(b)に示す
ように半導体素子3の電゛匝4と導体配線2とを一致さ
せ、半導体素子3を加圧し、配線基板1に押し当てる。Silicone, acrylic, etc. Next, as shown in FIG. 2(b), the cap 4 of the semiconductor element 3 and the conductor wiring 2 are aligned, and the semiconductor element 3 is pressed against the wiring board 1 by applying pressure.
電極4はムl、ムu、Cu等である。The electrode 4 is made of MuI, Mu, Cu, or the like.
この時、導体配線2上の、R脂6は周囲に押し出され、
半導体素子3の電極4と導体配線2は電気的に接触する
。次に半導体素子3を加圧体6によシ加圧した状態で上
部外方よシ紫外meを照射することに、よシ、半導体素
子3周縁の樹脂6を硬化させ、仮固定する。更に半導体
素子3を加圧しながら加熱することによ)、樹脂5全体
を硬化させ、この時半導体素子3の電極4と導体配線2
は樹脂6の接着力により電気的接続がなされ、・同時に
半導体素子3を配線基板1に固着することができる。At this time, the R fat 6 on the conductor wiring 2 is pushed out to the surroundings,
The electrode 4 of the semiconductor element 3 and the conductor wiring 2 are in electrical contact. Next, while the semiconductor element 3 is pressed by the pressurizing body 6, the upper part is irradiated with ultraviolet light from the outside to harden the resin 6 around the semiconductor element 3 and temporarily fix it. Furthermore, by heating the semiconductor element 3 while applying pressure), the entire resin 5 is cured, and at this time, the electrode 4 of the semiconductor element 3 and the conductor wiring 2 are cured.
An electrical connection is made by the adhesive force of the resin 6, and at the same time, the semiconductor element 3 can be fixed to the wiring board 1.
発明が解決しようとする課題
以上のように従来の技術では、半導体素子3の電極4を
配線基板1の導体配線2に直接接触させる方法であるた
め、多端子、狭ピッチの半導体素子3の実装に有利な方
法であるが、半導体素子3が加圧体6に対し傾きを生じ
た時半導体素子3は不均一に加圧され、そのひずみにょ
シ接読の信頼性が低下すると云う問題があった。Problems to be Solved by the Invention As described above, in the conventional technology, the electrodes 4 of the semiconductor element 3 are brought into direct contact with the conductor wiring 2 of the wiring board 1, so it is difficult to mount the semiconductor element 3 with multiple terminals and a narrow pitch. However, there is a problem in that when the semiconductor element 3 is tilted with respect to the pressurizing body 6, the semiconductor element 3 is pressed unevenly, and the reliability of close reading is reduced due to the distortion. Ta.
課題を解決するための手段
上記間厘点を解決するために本発明は、加圧部を加圧体
を0リングを介して押圧体で押圧する溝成としだもので
ある。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention employs a groove structure in which the pressing part is pressed by a pressing body through an O-ring.
作用
上記溝成によれば、弾性体であるOリングの圧縮ひずみ
によって加圧体で半導体素子を均一に加圧させることが
できるので、接、読の信頼性の高いものとなる。Effect: According to the above-mentioned groove structure, the compression strain of the O-ring, which is an elastic body, allows the pressurizing body to uniformly press the semiconductor element, resulting in highly reliable contact and reading.
実施e2り
以下、本発明の一実施例を第1図(&) 、(b)とと
もに説明する。Embodiment e2 Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1(&) and (b).
まず第1図(2L)に示すように、セラミック、ガラス
、エポキシ等よりなる配線基板11の半導体素子13を
固着する部分にエポキシ、シリコン。First, as shown in FIG. 1 (2L), epoxy or silicon is applied to the portion of the wiring board 11 made of ceramic, glass, epoxy, etc. to which the semiconductor element 13 is fixed.
アクリlし等よシなる絶縁性樹脂15を塗布する。An insulating resin 15 made of acrylic or the like is applied.
なお配線基板11上には導体配線12が設けられている
。この導体配線12ばcr−ムU、ムl。Note that conductor wiring 12 is provided on the wiring board 11. This conductor wiring 12Bcr-M U, Ml.
Ito等よりなる。次に第1図(b)に示すように半導
体素子13のムe、ムu、Cu 等よりなる突起状の電
極14と導体配線12を一致させ、加圧体16によシ加
圧する。この時加圧体16ばその押圧体17との間にO
リング18を介在させており0リング18の弾性によっ
て半導体j子13の1頂きを吸収し、平行な状態で加圧
体16で半導体素子13を加圧している。なお、加圧体
16はガラス、サファイア等の透明体で形成する。また
0リング18はシリコン、フッ素ゴム、GR等の弾性体
よりなる。加圧によシ導体配虜12上の樹脂15は周囲
に押し出され、電極14と導体配線12が当接し、この
状態で加圧体16を通して紫外線19を照射し、これに
よって半導体素子13の周碌部の支脂16を硬化させ仮
固定する。更に半導体素子13を加圧しながら加熱する
ことによっで半導体素子13の電極14と導体配線12
の電気的接続と半導体素子13の機械的保持が完了され
る。It consists of Ito et al. Next, as shown in FIG. 1(b), the protruding electrodes 14 made of Mu, Mu, Cu, etc. of the semiconductor element 13 are aligned with the conductor wiring 12, and pressure is applied by the pressurizing body 16. At this time, there is an O between the pressing body 16 and the pressing body 17.
A ring 18 is interposed, and the elasticity of the O-ring 18 absorbs one peak of the semiconductor element 13, and the pressure body 16 presses the semiconductor element 13 in a parallel state. Note that the pressurizing body 16 is formed of a transparent material such as glass or sapphire. Further, the O-ring 18 is made of an elastic material such as silicone, fluororubber, or GR. Due to the pressurization, the resin 15 on the conductor captive 12 is pushed out to the periphery, the electrode 14 and the conductor wiring 12 come into contact with each other, and in this state, ultraviolet rays 19 are irradiated through the pressurizing body 16, thereby exposing the peripheral portion of the semiconductor element 13. The supporting fat 16 is hardened and temporarily fixed. Furthermore, by heating the semiconductor element 13 while pressurizing it, the electrodes 14 of the semiconductor element 13 and the conductor wiring 12 are heated.
The electrical connection and mechanical holding of the semiconductor element 13 are completed.
なお、加圧体16にFe 、ムl 、 Cu 等より
なるリング20を設けることによシ、配線基板11によ
り反射された紫外1線19が0リング18を劣下させ、
頑き吸収能力が低下することを防いでいる。By providing the ring 20 made of Fe, Mul, Cu, etc. on the pressurizing body 16, the ultraviolet 1 rays 19 reflected by the wiring board 11 deteriorate the O ring 18,
It works hard to prevent the absorption capacity from decreasing.
発明の効果 本発明の効果を以下に示す。Effect of the invention The effects of the present invention are shown below.
(1)半導体素子を均一に加圧することにより、半導体
素子に与えるひずみをなくすることができるとともに、
導体配置sとの接続の信頼性の高いものとすることがで
きる。(1) By uniformly applying pressure to the semiconductor element, it is possible to eliminate strain on the semiconductor element, and
The connection with the conductor arrangement s can be made highly reliable.
+2) g外虜の照射と加圧が簡易な、溝道で実現で
き、量産性に優れたものとなる。+2) Irradiation and pressurization of the external prisoner can be easily achieved with a groove path, making it excellent for mass production.
第1図(2L) 、(b)は本発明の一実施例の半導体
装置で用いる配線基板の断面図と加圧体部の断面図、第
21B (a) 、(b)はともに従来の技術を示す断
面図である。
11・・・・・・配7腺基板、12・・・・・・導体配
線、13・・・・・半導体素子、14・・・・・・半導
体素子の電極、16・・・・・・絶縁性の樹脂、18・
・・・・・加圧体、17・・・・・・加圧体の押圧体、
18・・・・・・0リング、19・・・・・・紫外1線
、20・・・・・・金属リング。
MI図FIGS. 1(2L) and (b) are cross-sectional views of a wiring board and a pressurizing body used in a semiconductor device according to an embodiment of the present invention, and FIGS. 21B (a) and (b) are both conventional techniques. FIG. 11... Circuit board, 12... Conductor wiring, 13... Semiconductor element, 14... Electrode of semiconductor element, 16... Insulating resin, 18.
...pressure body, 17...pressure body of pressurization body,
18...0 ring, 19...ultraviolet 1 ray, 20...metal ring. MI diagram
Claims (1)
た加圧体と、この加圧体をOリングを介して半導体素子
に加圧する押圧体とを備えた半導体実装装置。A semiconductor mounting device comprising: a pressure member having one end surface serving as a pressure surface and the other end surface serving as a surface for transmitting ultraviolet rays; and a press member that presses the pressure member against a semiconductor element via an O-ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1140476A JPH034546A (en) | 1989-06-01 | 1989-06-01 | Semiconductor mounting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1140476A JPH034546A (en) | 1989-06-01 | 1989-06-01 | Semiconductor mounting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH034546A true JPH034546A (en) | 1991-01-10 |
| JPH0558660B2 JPH0558660B2 (en) | 1993-08-27 |
Family
ID=15269495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1140476A Granted JPH034546A (en) | 1989-06-01 | 1989-06-01 | Semiconductor mounting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH034546A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5296063A (en) * | 1990-03-20 | 1994-03-22 | Sharp Kabushiki Kaisha | Method for mounting a semiconductor device |
| US5316610A (en) * | 1991-12-26 | 1994-05-31 | Matsushita Electric Industrial Co., Ltd. | Bonding apparatus |
| WO2000011731A1 (en) * | 1998-08-21 | 2000-03-02 | Eveready Battery Company, Inc. | Battery having printed label |
| US7186584B2 (en) | 2002-03-06 | 2007-03-06 | Seiko Epson Corporation | Integrated circuit chip, electronic device and method of manufacturing the same, and electronic instrument |
| EP1993124A4 (en) * | 2006-03-07 | 2009-04-01 | Sony Chem & Inf Device Corp | ASSEMBLY METHOD, CARD WITH ELECTRICAL COMPONENT AND ELECTRICAL APPARATUS |
| JP2010178667A (en) * | 2009-02-05 | 2010-08-19 | Nissin Frozen Foods Co Ltd | Frozen seasoning liquid pack, frozen noodle containing the same, and method for producing the frozen noodle |
-
1989
- 1989-06-01 JP JP1140476A patent/JPH034546A/en active Granted
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5296063A (en) * | 1990-03-20 | 1994-03-22 | Sharp Kabushiki Kaisha | Method for mounting a semiconductor device |
| US5316610A (en) * | 1991-12-26 | 1994-05-31 | Matsushita Electric Industrial Co., Ltd. | Bonding apparatus |
| WO2000011731A1 (en) * | 1998-08-21 | 2000-03-02 | Eveready Battery Company, Inc. | Battery having printed label |
| US7186584B2 (en) | 2002-03-06 | 2007-03-06 | Seiko Epson Corporation | Integrated circuit chip, electronic device and method of manufacturing the same, and electronic instrument |
| EP1993124A4 (en) * | 2006-03-07 | 2009-04-01 | Sony Chem & Inf Device Corp | ASSEMBLY METHOD, CARD WITH ELECTRICAL COMPONENT AND ELECTRICAL APPARATUS |
| JP2010178667A (en) * | 2009-02-05 | 2010-08-19 | Nissin Frozen Foods Co Ltd | Frozen seasoning liquid pack, frozen noodle containing the same, and method for producing the frozen noodle |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0558660B2 (en) | 1993-08-27 |
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