JPH0346881U - - Google Patents

Info

Publication number
JPH0346881U
JPH0346881U JP10697689U JP10697689U JPH0346881U JP H0346881 U JPH0346881 U JP H0346881U JP 10697689 U JP10697689 U JP 10697689U JP 10697689 U JP10697689 U JP 10697689U JP H0346881 U JPH0346881 U JP H0346881U
Authority
JP
Japan
Prior art keywords
output signal
input
signal
variable gain
gain amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10697689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10697689U priority Critical patent/JPH0346881U/ja
Publication of JPH0346881U publication Critical patent/JPH0346881U/ja
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例を示すブロツク図
、第2図は従来の装置の一実施例を示すブロツク
図であり、図において、1……可変利得増幅器A
、2……周波数変換器、3……可変利得増幅器B
、4……不要波除去フイルタ、5……可変利得増
幅器C、6……検波回路、7……ビデオ増幅器、
8……AGC回路、9……ドライバ回路C、10
……ドライバ回路B、11……ドライバ回路A、
12……パワーデバイダ、13……飽和検出回路
、14……AGC回路である。なお、各図中同一
符号は同一、又は相当部分を示す。
FIG. 1 is a block diagram showing an embodiment of this invention, and FIG. 2 is a block diagram showing an embodiment of a conventional device.
, 2... Frequency converter, 3... Variable gain amplifier B
, 4...Unwanted wave removal filter, 5...Variable gain amplifier C, 6...Detection circuit, 7...Video amplifier,
8...AGC circuit, 9...Driver circuit C, 10
...Driver circuit B, 11...Driver circuit A,
12...Power divider, 13...Saturation detection circuit, 14...AGC circuit. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] レーダ装置の受信信号が入力される可変利得増
幅器Aと、この出力信号を中間周波数信号に変換
する周波数変換器と、この周波数変換器の出力信
号が入力される可変利得増幅器Bと、この可変利
得増幅器Bの出力信号が入力され2つの出力端子
を持つパワーデバイダと、このパワーデバイダの
一つの出力端子の出力信号が入力される不要波除
去フイルタと、この不要波除去フイルタの出力信
号が入力される可変利得増幅器Cと、この可変利
得増幅器Cの出力信号が入力され、その信号をビ
デオ信号に変換する検波回路と、この検波回路の
出力信号が入力され2つの出力端子を持ち、その
一つを信号処理用に送り出し、もう一つの出力信
号をAGC回路へ入力しているビデオ増幅器と、
上記AGC回路の出力信号により上記可変利得増
幅器Aの利得を制御しているドライバ回路Aと、
上記AGC回路の出力信号により上記可変利得増
幅器Bの利得を制御しているドライバ回路Bと、
上記AGC回路の出力信号により上記可変利得増
幅器Cの利得を制御しているドライバ回路Cと、
上記パワーデバイダのもう一つの出力信号が入力
され、その出力信号を上記AGC回路に入力して
いる飽和検出回路とで構成されていることを特徴
とした追尾レーダ受信機。
A variable gain amplifier A to which the received signal of the radar device is input, a frequency converter which converts this output signal to an intermediate frequency signal, a variable gain amplifier B to which the output signal of this frequency converter is input, and this variable gain A power divider to which the output signal of amplifier B is input and has two output terminals, an unnecessary wave removal filter to which the output signal of one output terminal of this power divider is input, and an output signal of this unnecessary wave removal filter to which the output signal is input. a variable gain amplifier C, a detection circuit to which the output signal of the variable gain amplifier C is input and converts the signal into a video signal, and a detection circuit to which the output signal of the detection circuit is input, one of which has two output terminals; a video amplifier that sends out a signal for signal processing and inputs another output signal to an AGC circuit;
a driver circuit A that controls the gain of the variable gain amplifier A based on the output signal of the AGC circuit;
a driver circuit B controlling the gain of the variable gain amplifier B based on the output signal of the AGC circuit;
a driver circuit C controlling the gain of the variable gain amplifier C based on the output signal of the AGC circuit;
A tracking radar receiver comprising: a saturation detection circuit to which another output signal of the power divider is input, and the output signal is input to the AGC circuit.
JP10697689U 1989-09-12 1989-09-12 Pending JPH0346881U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10697689U JPH0346881U (en) 1989-09-12 1989-09-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10697689U JPH0346881U (en) 1989-09-12 1989-09-12

Publications (1)

Publication Number Publication Date
JPH0346881U true JPH0346881U (en) 1991-04-30

Family

ID=31655694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10697689U Pending JPH0346881U (en) 1989-09-12 1989-09-12

Country Status (1)

Country Link
JP (1) JPH0346881U (en)

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