JPH0347628B2 - - Google Patents

Info

Publication number
JPH0347628B2
JPH0347628B2 JP14300281A JP14300281A JPH0347628B2 JP H0347628 B2 JPH0347628 B2 JP H0347628B2 JP 14300281 A JP14300281 A JP 14300281A JP 14300281 A JP14300281 A JP 14300281A JP H0347628 B2 JPH0347628 B2 JP H0347628B2
Authority
JP
Japan
Prior art keywords
coefficient
signal
add
delay
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14300281A
Other languages
Japanese (ja)
Other versions
JPS5844880A (en
Inventor
Masaru Hirono
Shizuka Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HITACHI ELECTRONICS
Original Assignee
HITACHI ELECTRONICS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HITACHI ELECTRONICS filed Critical HITACHI ELECTRONICS
Priority to JP14300281A priority Critical patent/JPS5844880A/en
Publication of JPS5844880A publication Critical patent/JPS5844880A/en
Publication of JPH0347628B2 publication Critical patent/JPH0347628B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00Details of colour television systems
    • H04N9/64Circuits for processing colour signals
    • H04N9/646Circuits for processing colour signals for image enhancement, e.g. vertical detail restoration, cross-colour elimination, contour correction, chrominance trapping filters

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、カラーテレビジヨンカメラ(以下、
カメラ)等のテレビジヨン信号回路において、色
差信号、色信号等における雑音成分を低減し、テ
レビジヨン信号の信号対雑音比を大幅に向上させ
る雑音低減回路に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a color television camera (hereinafter referred to as
The present invention relates to a noise reduction circuit that reduces noise components in color difference signals, chrominance signals, etc. in television signal circuits such as cameras) and significantly improves the signal-to-noise ratio of television signals.

〔従来の技術〕[Conventional technology]

第2図は、カメラに例を取つた場合の従来例を
示すブロツク図であり、各色撮像管等により得た
各原色信号R(赤),G(緑),B(青)はマトリク
ス回路MTXへ与えられ、こゝにおいて、輝度信
号Yおよび色差信号R−Y,B−Yとなつたう
え、色差信号R−B,B−Yは、各々が低域波
器LPF1,LPF2により、雑音成分抑圧のための帯
域制限を受け、加算器ADD1,ADD2および遅延
回路DL1,DL2へ与えられる。
Fig. 2 is a block diagram showing a conventional example when taking a camera as an example, and each primary color signal R (red), G (green), B (blue) obtained from each color image pickup tube etc. is connected to a matrix circuit MTX. Here, the luminance signal Y and the color difference signals R-Y, B-Y are generated, and the color difference signals R-B, B-Y are each passed through the low frequency filters LPF 1 and LPF 2 . The signal is subjected to band restriction for noise component suppression and is applied to adders ADD 1 and ADD 2 and delay circuits DL 1 and DL 2 .

また、遅延回路DL1,DL2の各出力は、加算器
ADD1,ADD2へ直接与えられると共に、同様の
遅延回路DL3,DL4を介して加算器ADD1
ADD2へ与えられるものとなつており、各遅延回
路DL1〜DL4が、各々1走査線分すなわち1H(H
は、水平走査線の始めから、つぎの水平走査線の
始めまでの期間)分の遅延時間を有するため、加
算器ADD1,ADD2においては、現在の色差信号
R−Y,B−Yと、1H前の同信号R−Y,R−
Yと、2H前の同信号R−Y,B−Yとが各個に
加算される。
In addition, each output of delay circuits DL 1 and DL 2 is connected to an adder.
It is directly applied to ADD 1 and ADD 2 , and is also applied to adders ADD 1 and ADD 2 via similar delay circuits DL 3 and DL 4 .
ADD 2 , and each delay circuit DL 1 to DL 4 provides a signal for one scanning line, that is, 1H (H
has a delay time of (period from the beginning of the horizontal scanning line to the beginning of the next horizontal scanning line), so in the adders ADD 1 and ADD 2 , the current color difference signals R-Y, B-Y and , the same signal RY, R- 1H ago
Y and the same signals R-Y and B-Y from 2H ago are added individually.

このため、加算器ADD1,ADD2の出力として
は、色差信号R−Y,B−Yを各々3H分づゝ加
算した信号が得られ、一般に映像信号は映像面の
垂直方向に対して相関性を有することにより、映
像成分の電圧が3倍となるのに対し、雑音成分の
相関性は不特定であり、電力平均の√13となる。
Therefore, the output of the adders ADD 1 and ADD 2 is a signal obtained by adding the color difference signals R-Y and B-Y by 3H each, and generally the video signal has a correlation with respect to the vertical direction of the image plane. By having this property, the voltage of the video component is tripled, whereas the correlation of the noise component is unspecified and becomes √13 of the power average.

したがつて、映像成分と雑音成分との差が拡大
し、信号対雑音比が改善される。
Therefore, the difference between the video component and the noise component is increased, and the signal-to-noise ratio is improved.

信号対雑音比の改善された加算器ADD1
ADD2の各出力は、二重平衡変調器等の変調器
MOD1,MOD2へ与えられ、副搬送波SCを移相
器PS1により90゜移相したもの、および移相器PS1
を介さないものを各個に変調し、色信号となつて
から加算器ADD3へ与えられる。
Adder ADD 1 with improved signal-to-noise ratio,
Each output of ADD 2 can be connected to a modulator such as a double balanced modulator.
MOD 1 and MOD 2 , subcarrier SC shifted by 90° by phase shifter PS 1 , and phase shifter PS 1.
The signals that do not go through the chrominance signal are individually modulated to become color signals, which are then applied to the adder ADD 3 .

加算器ADD3には、マトリクス回路MTXから
の輝度信号Yおよび同期信号SYNが与えられて
いると共に、副搬送波SCに基づきバースト信号
発生器BGにおいて発生したバースト信号が与え
られており、これらが合成されたうえ、テレビジ
ヨン標準方式のテレビジヨン信号SVとして送出
される。
The adder ADD 3 is supplied with the luminance signal Y and synchronization signal SYN from the matrix circuit MTX, and is also supplied with the burst signal generated in the burst signal generator BG based on the subcarrier SC, and these are synthesized. In addition, it is transmitted as a television signal SV in the standard television format.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、第2図の構成による場合には、雑音低
減に用いる遅延回路DL1〜DL4を4回路必要と
し、これにデイジタルメモリを用いれば、記憶容
量の大きなものを要すると共に、データのアクセ
スを制御する周辺回路、およびアナログ・デイジ
タル変換器、デイジタル・アナログ変換器等を要
するため、高価となるうえ、回路構成が複雑化す
る等の欠点を生ずる。
However, in the case of the configuration shown in Fig. 2, four delay circuits DL 1 to DL 4 are required for noise reduction, and if digital memory is used for this, a large storage capacity is required and data access is difficult. Since peripheral circuits for control, an analog-to-digital converter, a digital-to-analog converter, etc. are required, it is expensive and has drawbacks such as a complicated circuit configuration.

また、遅延回路DL1〜DL4にガラス遅延回路等
の超音波遅延素子を用いれば、伝送周波数帯域の
関係上、色差信号R−Y,B−Yをそのまゝ与え
ることができず、一旦周波数変換を行なつてから
遅延素子へ与えたうえ、これの出力を再び元の周
波数帯域へ復調する必要があり、この場合も回路
構成の複雑化により高価となる欠点を生ずる。
Furthermore, if ultrasonic delay elements such as glass delay circuits are used in the delay circuits DL 1 to DL 4 , the color difference signals R-Y and B-Y cannot be given as they are due to the transmission frequency band. It is necessary to perform frequency conversion and then apply it to the delay element, and then demodulate the output again to the original frequency band, which again has the drawback of complicating the circuit configuration and increasing the cost.

なお、以上の各欠点のほかに、遅延回路DL1
DL4による信号の遅延成分が存在し、本来は無信
号状態となるべき垂直ブランキング期間へ遅延成
分が現われ、テレビジヨン標準方式上の規定に反
するものになると共に、種々の障害を与える欠点
も生じている。
In addition to the above-mentioned drawbacks, the delay circuit DL 1 ~
There is a signal delay component due to DL 4 , and the delay component appears in the vertical blanking period, which should normally be a no-signal state, which violates the regulations of the television standard system and also has the disadvantage of causing various problems. It is occurring.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、従来のかゝる欠点を根本的に排除す
る目的を有し、単一の遅延回路へ反復して同一の
信号を通過させるものとし、かつ、垂直ブランキ
ングパルスに応じて通過する信号を阻止すること
により、構成の簡略化と共に、垂直ブランキング
期間へ遅延成分が現われないものとした極めて効
果的な、色信号雑音低減回路を提供するものであ
る。
The present invention has the purpose of fundamentally eliminating such drawbacks of the conventional art, in which the same signal is repeatedly passed through a single delay circuit, and the signal to be passed in response to a vertical blanking pulse is By preventing this, it is possible to provide an extremely effective color signal noise reduction circuit that has a simplified configuration and prevents delay components from appearing in the vertical blanking period.

〔実施例〕〔Example〕

以下、実施例を示す第1図以降により本発明の
詳細を説明する。
The details of the present invention will be explained below with reference to FIG. 1 and subsequent figures showing embodiments.

第1図は第2図と同様のブロツク図であるが、
低域波器LPF1,LPF2を介した色差信号R−
Y,B−Yを、第1の係数器FM1,FM2へ与え、
こゝにおいて、所定の係数1−K(ただし、0<
K<1)を色差信号R−B,B−Yへ乗じたう
え、加算器ADD11,ADD12へ与えている。
Figure 1 is a block diagram similar to Figure 2, but
Color difference signal R- via low-pass filters LPF 1 and LPF 2
Give Y, BY to the first coefficient multipliers FM 1 and FM 2 ,
Here, a predetermined coefficient 1-K (however, 0<
The color difference signals R-B and B-Y are multiplied by K<1) and then supplied to the adders ADD 11 and ADD 12 .

また、加算器ADD11,ADD12の出力は、変調
器MOD1,MOD2へ送出されると共に、遅延回路
DL11,DL12へ与えられており、加算器ADD11
ADD12の各出力を入力として遅延回路DL11
DL12が1H分の遅延時間を与えたうえ、第2の係
数器FM3,FM4へ入力信号として与える。
Furthermore, the outputs of adders ADD 11 and ADD 12 are sent to modulators MOD 1 and MOD 2 , and are also sent to delay circuits.
It is given to DL 11 and DL 12 , and the adder ADD 11 ,
Delay circuit DL 11 with each output of ADD 12 as input,
DL 12 provides a delay time of 1H and provides it as an input signal to the second coefficient multipliers FM 3 and FM 4 .

係数器FM3,FM4は、係数器FM1,FM2の係
数1−Kに対して補数の関係を有する係数Kを入
力信号へ乗ずるものであり、これの出力が加算器
ADD11,ADD12へ与えられ、加算器ADD11
ADD12においては、各係数器FM1とFM3および
FM2とFM4との各出力が各々加算される。
The coefficient multipliers FM 3 and FM 4 multiply the input signal by a coefficient K that has a complementary relation to the coefficient 1-K of the coefficient multipliers FM 1 and FM 2 , and the output of these multiplies the input signal.
Provided to adders ADD 11 , ADD 12 ,
In ADD 12 , each coefficient multiplier FM 1 and FM 3 and
The respective outputs of FM 2 and FM 4 are added together.

このため、係数1−Kを乗ぜられた色差信号R
−Y,B−Yは、1H分の遅延と係数Kの乗算と
を受けてから加算され、これを無限に反復するも
のとなり、第2図と同様の雑音低減効果を呈す
る。
Therefore, the color difference signal R multiplied by the coefficient 1-K
-Y and B-Y are added after being delayed by 1H and multiplied by a coefficient K, and this is repeated infinitely, providing the same noise reduction effect as in FIG. 2.

すなわち、係数器FM1,FM2の入力信号をSi
とすれば、加算器ADD11,ADD12の出力Soは、
次式により与えられる。
In other words, the input signals of coefficient multipliers FM 1 and FM 2 are
Then, the output So of adders ADD 11 and ADD 12 is
It is given by the following equation.

So=(1-K)Si+(1-K)Si・K+(1-K)Si・K2+(1-K)Si・K3
+…=Si(1−Kn)……(1) また、雑音成分の電力Pnは、次式により示さ
れる。
So=(1-K)Si+(1-K)Si・K+(1-K)Si・K 2 +(1-K)Si・K 3
+...=Si(1- Kn )...(1) Moreover, the power Pn of the noise component is expressed by the following equation.

したがつて、映像成分は(1)式により示されると
おり0<K<1の場合、ほぼ一定であるが、例え
ばK=0.5とするとき、雑音成分は(2)式から√13
となり、信号対雑音比が改善される。
Therefore, as shown by equation (1), the video component is almost constant when 0<K<1, but when K=0.5, for example, the noise component is √13 from equation (2).
As a result, the signal-to-noise ratio is improved.

なお、第1図においては、同期信号SYNと同
様に同期信号発生器等から供給される垂直ブラン
キングパルスVBLが、各係数器FM1〜FM4へ与
えられており、これによつて各係数器FM1
FM4の乗ずる係数Kの値を減少させる結果、垂
直ブランキング期間において係数器FM1,FM2
の出力レベルを増大させ、係数器FM3,FM4
出力レベルを低下させている。
In FIG. 1, a vertical blanking pulse VBL supplied from a synchronizing signal generator or the like in the same way as the synchronizing signal SYN is given to each coefficient unit FM 1 to FM 4 , and thereby each coefficient Instrument FM 1 ~
As a result of decreasing the value of the coefficient K to which FM 4 is multiplied, the coefficient multipliers FM 1 and FM 2 increase during the vertical blanking period.
The output level of coefficient multipliers FM 3 and FM 4 is decreased.

このため、遅延回路DL11,DL12を介して加算
器ADD11,ADD12を循環する信号が減少し、加
算器ADD11,ADD12の入力は、ほぼ係数器FM1
FM2の出力のみとなり、垂直ブランキング期間
において遅延成分が現われず、無信号状態とな
る。
Therefore, the signals circulating through the adders ADD 11 and ADD 12 via the delay circuits DL 11 and DL 12 are reduced, and the inputs of the adders ADD 11 and ADD 12 are almost the same as those of the coefficient multipliers FM 1 ,
Only FM 2 is output, and no delay component appears during the vertical blanking period, resulting in a no-signal state.

なお、以上の雑音低減回路は、カメラのみなら
ず、条件に応じ、カメラ制御装置、カラーエンコ
ーダ等の各種映像機器へ設けても同様であり、遅
延回路DL11,DL12には、各信号をデイジタル信
号化のうえ、メモリ、シフトレジスタ等を用いて
もよく、場合によつては係数器FM3,FM4のみ
を垂直ブランキングパルスVBLにより制御して
もよい等、種々の変形が自在である。
Note that the above noise reduction circuit can be installed not only in cameras but also in various video equipment such as camera control devices and color encoders depending on the conditions.The delay circuits DL 11 and DL 12 are configured to In addition to converting into digital signals, memory, shift registers, etc. may be used, and in some cases, only the coefficient multipliers FM 3 and FM 4 may be controlled by the vertical blanking pulse VBL. Various modifications are possible. be.

〔発明の効果〕〔Effect of the invention〕

以上の説明により明らかなとおり本発明によれ
ば、各単一の遅延回路により色差信号および色信
号の雑音が低減されると同時に、垂直ブランキン
グ期間が無信号状態となり、再生映像の画質向上
および、テレビジヨン標準方式への適合性確保が
達せられると共に、構成の簡略化および価格の低
減が容易に実現するため、カメラおよび各種の映
像機器において顕著な効果を呈する。
As is clear from the above description, according to the present invention, each single delay circuit reduces color difference signals and color signal noise, and at the same time, the vertical blanking period becomes a no-signal state, thereby improving the image quality of reproduced video. , it is possible to ensure compatibility with the television standard system, and also to easily realize simplification of structure and reduction in price, and therefore it exhibits remarkable effects in cameras and various video equipment.

【図面の簡単な説明】[Brief explanation of drawings]

第2図は従来例のブロツク図、第1図は本発明
の実施例を示すブロツク図である。 FM1,FM2……第1の係数器、FM3,FM4
…第2の係数器、ADD11,ADD12……加算器、
DL11,DL12……遅延回路、VBL……垂直ブラン
キングパルス。
FIG. 2 is a block diagram of a conventional example, and FIG. 1 is a block diagram showing an embodiment of the present invention. FM 1 , FM 2 ... first coefficient multiplier, FM 3 , FM 4 ...
...Second coefficient unit, ADD 11 , ADD 12 ...Adder,
DL 11 , DL 12 ...Delay circuit, VBL...Vertical blanking pulse.

Claims (1)

【特許請求の範囲】[Claims] 1 色差信号へ所定の計数を乗ずる第1の係数器
と、前記所定の係数と補数の関係を有する係数を
入力信号へ乗ずると共にブランキングパルスに応
じて前記係数の値が減少する第2の係数器と、前
記第1および第2の係数器の各出力を加算する加
算器と、該加算器の出力を入力として少なくとも
1走査線分の遅延時間を与えたうえ前記第2の係
数器へ入力信号として与える遅延回路とを設けた
ことを特徴とする色信号雑音低減回路。
1. A first coefficient multiplier that multiplies a color difference signal by a predetermined coefficient; and a second coefficient that multiplies an input signal by a coefficient having a complementary relationship with the predetermined coefficient, and the value of the coefficient decreases in response to a blanking pulse. an adder for adding the respective outputs of the first and second coefficient multipliers; the output of the adder is inputted and given a delay time of at least one scanning line, and then input to the second coefficient multiplier; 1. A color signal noise reduction circuit comprising a delay circuit that provides a signal.
JP14300281A 1981-09-10 1981-09-10 Chroma signal noise reduction circuit Granted JPS5844880A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14300281A JPS5844880A (en) 1981-09-10 1981-09-10 Chroma signal noise reduction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14300281A JPS5844880A (en) 1981-09-10 1981-09-10 Chroma signal noise reduction circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP30877190A Division JPH03174889A (en) 1990-11-16 1990-11-16 Color signal noise reduction circuit

Publications (2)

Publication Number Publication Date
JPS5844880A JPS5844880A (en) 1983-03-15
JPH0347628B2 true JPH0347628B2 (en) 1991-07-19

Family

ID=15328657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14300281A Granted JPS5844880A (en) 1981-09-10 1981-09-10 Chroma signal noise reduction circuit

Country Status (1)

Country Link
JP (1) JPS5844880A (en)

Also Published As

Publication number Publication date
JPS5844880A (en) 1983-03-15

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