JPH0348329U - - Google Patents

Info

Publication number
JPH0348329U
JPH0348329U JP10705889U JP10705889U JPH0348329U JP H0348329 U JPH0348329 U JP H0348329U JP 10705889 U JP10705889 U JP 10705889U JP 10705889 U JP10705889 U JP 10705889U JP H0348329 U JPH0348329 U JP H0348329U
Authority
JP
Japan
Prior art keywords
circuit board
electronic circuit
surge current
discharge
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10705889U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10705889U priority Critical patent/JPH0348329U/ja
Publication of JPH0348329U publication Critical patent/JPH0348329U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structure Of Printed Boards (AREA)
  • Emergency Protection Circuit Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図乃至第３図は本考案の一実施例を示し、
第１図は電子回路基板を内装する電子チユーナの
一部切欠底面図、第２図ａ，ｂ，ｃ，ｄは夫々本
考案の第１、第２、第３、第４の実施例を示す電
子回路基板の一部切欠底面図、第３図は入力フイ
ルタ部の回路図であり、第４図は従来例を示す入
力フイルタ部の回路図である。 ８……電子回路基板、９……グラウンドパター
ン、１０……入力端子パターン、１６ａ，１６ｂ
，１６ｃ……放電用ランド。 1 to 3 show an embodiment of the present invention,
Fig. 1 is a partially cutaway bottom view of an electronic tuner incorporating an electronic circuit board, and Fig. 2 a, b, c, and d show the first, second, third, and fourth embodiments of the present invention, respectively. A partially cutaway bottom view of the electronic circuit board, FIG. 3 is a circuit diagram of the input filter section, and FIG. 4 is a circuit diagram of the input filter section showing a conventional example. 8...Electronic circuit board, 9...Ground pattern, 10...Input terminal pattern, 16a, 16b
, 16c...Land for discharge.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電子回路基板の入力端子パターンとグラウンド
パターンとにサージ電流の放電用ランドを形成し
、且つ該放電用ランドを接近して対向させたこと
を特徴とする電子回路基板に於けるサージ電流バ
イパス装置。 A surge current bypass device for an electronic circuit board, characterized in that a surge current discharge land is formed between an input terminal pattern and a ground pattern of the electronic circuit board, and the discharge lands are closely opposed to each other.
JP10705889U 1989-09-12 1989-09-12 Pending JPH0348329U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10705889U JPH0348329U (en) 1989-09-12 1989-09-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10705889U JPH0348329U (en) 1989-09-12 1989-09-12

Publications (1)

Publication Number Publication Date
JPH0348329U true JPH0348329U (en) 1991-05-09

Family

ID=31655776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10705889U Pending JPH0348329U (en) 1989-09-12 1989-09-12

Country Status (1)

Country Link
JP (1) JPH0348329U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156955A (en) * 2004-10-26 2006-06-15 Denso Corp Circuit board and electronic circuit device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63108689A (en) * 1986-10-23 1988-05-13 株式会社ニコン Destruction prevention device for circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63108689A (en) * 1986-10-23 1988-05-13 株式会社ニコン Destruction prevention device for circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156955A (en) * 2004-10-26 2006-06-15 Denso Corp Circuit board and electronic circuit device

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