JPH0348640Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to an electronic musical instrument in which a digital envelope waveform compatible with time division channels can be easily obtained using coefficients related to attack time and decay time. Conventional envelope signal generation circuit systems for electronic musical instruments include an analog system that utilizes the charging and discharging characteristics of a time constant circuit consisting of a capacitor and a resistor, and a digital system that stores quantization step information. However, in the analog method, the envelope is
In order to prepare various characteristics for each part of ADSR (Attack, Decay, Sustain, Release),
There is a type of switch that combines a large number of resistors, diodes, and changeover switches, but the circuit configuration is complicated. In contrast, digital methods have the problem that in order to increase the number of quantization steps and provide various attack time and decay time characteristics, the storage capacity for storing this information becomes enormous. It was hot. An object of the present invention is to provide an electronic musical instrument that can obtain envelope waveforms of various attack times and decay times corresponding to time division channels with a small storage capacity. In order to achieve the above object, the electronic musical instrument of the present invention includes a timing generation circuit that generates timing pulses, an address counter driven by the timing generation circuit, and an address pulse of the address counter to determine the attack decay time. an attack decay coefficient memory from which a coefficient to be controlled is read; an adder for adding the attack decay coefficient from the attack decay coefficient memory and a value read from the storage circuit; and an adder for storing the addition result and returning it to the addition circuit. and the storage circuit for reading data, and outputs a cumulative output signal of the attack decay coefficient from the adder in response to a timing pulse of the timing generating circuit and an address pulse of the address counter, and the cumulative output is set to a predetermined value. an accumulator that detects that the value has reached a value and outputs each end signal of the attack decay; and a coefficient given to the accumulator by the attack signal from the outside and each end signal of the attack decay from the accumulator. an envelope control circuit which uses an attack coefficient when attacking and a decay coefficient when decaying; an envelope waveform table that stores the amplitude of an envelope waveform having a logarithmic curve and reads it out using the cumulative output signal; When corresponding to each channel using an EX-OR circuit that inverts or non-inverts an output signal, a D/A converter that converts the output signal of the EX-OR circuit into an analog waveform, and an output signal of the address counter. a channel decoder that outputs a division multiplexed signal; and an analog multiplexer that time-divides and distributes the analog output of the D/A converter to each corresponding channel; make use of,
After each channel is time-divisionally operated and an envelope waveform corresponding to the attack of each channel is formed using the address from the accumulator, the readout of the attack/decay coefficient memory is controlled by the decay period output signal from the accumulator. At the same time, the envelope waveform data from the envelope waveform table is inverted by the EX-OR circuit to form a decay waveform, and the envelope control circuit terminates the accumulation by a decay end signal from the accumulator. After that, for each corresponding channel, the channel decoder obtains a time-division multiplexed signal for each channel from the output signal of the address counter, and the analog multiplexer divides and outputs the time-division multiplexed signal. It is characterized by the fact that it is made to do so. The present invention will be described in detail below with reference to examples. FIG. 1 is a schematic explanatory diagram of an embodiment of the present invention.
The figure shows an example used in the sound generation mechanism of an electronic musical instrument.
That is, the key press information obtained by detecting the closing of the key switch 1 by the key assigner 2 is input to the tone generating circuit 3, and a tone corresponding to the key press is generated. Also,
Assuming that the key assigner is capable of detecting up to 16 notes, the information of key switch 1 will be channel CH1.
- Outputs a signal indicating which of CH16 is stored, that is, an attack signal. The envelope generating circuit 4, which is the main part of the present invention, generates a musical tone signal with a desired envelope waveform created by the tone signal from the tone generating circuit 3 and the attack signal from the key assigner 2, and generates a musical tone signal with a desired envelope waveform in response to a key press. Sound is emitted from the sound device 5. FIG. 2 is a schematic explanatory diagram of another embodiment of the present invention, in which the present invention is applied to a rhythm generating device. That is, by the select switch 6,
A rhythm is selected and a rhythm pattern corresponding to the selected rhythm is output to the rhythm pattern generation circuit 7. The next envelope generating circuit 4 receives the rhythm pattern signal, creates a desired envelope waveform, and outputs the rhythm sound of the sound source 8 corresponding to the rhythm pattern. In this case, the rhythm pattern signal corresponds to the attack signal in FIG. FIG. 3 is an explanatory diagram of an embodiment of the envelope generating circuit 4, which is a main part of the rhythm generating circuit shown in FIG.
Here, the number of sound sources is 16, and 16 channels are created.
It is assumed that the envelope waveform is formed in a time-division manner. In the figure, a rhythm pattern signal (hereinafter referred to as an attack signal) from a rhythm pattern generator is input to an envelope control circuit 17, and attack and decay timings of the envelope waveform are formed by signals C1 and C2, which will be described later. A channel designation signal from a channel decoder 21 designated via an address counter 20 driven by 19 is applied to an envelope control circuit 17, and the designated address signal is input to an attack decay coefficient memory 13 through an OR circuit 15. The attack decay coefficient memory 13 reads attack and decay coefficients to be described later based on the address from the address counter 20, and the adder
It is applied to an accumulator 11 consisting of a gate circuit, a register, and a memory circuit (RAM). In the accumulator 11, an address counter 20
, and a channel designation signal given from the envelope control circuit 17 via the OR circuit 16, and the addition coefficients are accumulated in a manner described later to produce 8-bit binary address information as an accumulated output signal. It is output and given to the envelope waveform table 14. The processing data of accumulator 11 is 10
In addition to the 8-bit address data, carry signals C1 and C2 are included. When 8-bit address data is sent to the envelope waveform table 14, the upper 5 bits are used as the address, and the lower 3 bits are truncated. Also signal C
1 indicates that the attack period has ended, and the signal C
2 indicates that decay has ended, and is sent to the envelope control circuit 17 mentioned above. In this accumulator 11, accumulated output signals of 16 envelope waveforms corresponding to 16 channels are obtained. The envelope time T between the rise and fall of the envelope waveform accumulated by the attack and decay coefficients stored in the attack decay coefficient memory 13 is determined by the following formula. T=N×W/ _CL /n×A _AD where N: Number of channels W: Number of words A _AD ; Envelope addition coefficient C _L ; Clock frequency n: Timing frequency division number In the example, N=16, W=32 , n = 4, then T = 512 x 4/C _L × A _AD Now, if C _L = 10KHz, then A _AD = 1/2 ³ , T = 1.64 seconds, A _AD = 1, T = 0.20 seconds. Become. As above, envelope addition coefficient value A _AD
This determines the rise and fall times of attack and decay. The attack decay coefficient memory 13 stores attack and decay addition coefficient values A _AD corresponding to 16 sound sources. Table 1 shows the coefficient values for attack and decay.
An example of the cumulative time T (seconds) of A _AD is shown.

【table】

【table】

[Table] The envelope waveform table 14 stores a 32-word envelope waveform whose address is a 5-bit cumulative output signal. Table 2 shows one example. This value was determined using the formula below. If the envelope waveform table 14 is a 32-word, 8-bit fixed memory (ROM), Y: Number of bits W: Number of words (0 to 31) This waveform is shown in FIG. 4 and is shared by both the attack and decay waveforms. The above example uses 32 words with the upper 5 bits of the output signal of the accumulator 11 as the address, but by using 6 or more bits, the number of quantization steps can be made denser. Next, the contents of the envelope waveform table 14 are input into the exclusive (EX) OR circuit 22, and when the signal C1 becomes a higher level than the initial value of the next cycle after the 32 words of the attack waveform are completed by the signal C1, the contents of the envelope waveform table 14 are input. The data is inverted to form a decay waveform. FIG. 5a shows the inversion of the attack and decay waveforms, signal C1 in FIG. 5b indicates the end of attack, and signal C2 in FIG. 5c indicates the end of decay. In this case, the same contents of the envelope waveform table 14 are used as a common waveform for attack and decay. next
The output of the EX-OR circuit 22 is converted into an analog quantity through the D/A converter 23, and the time-divided analog data is distributed to each channel by the next analog multiplexer 24. Holds analog data. FIG. 6 is a detailed circuit example of the embodiment shown in FIG. 3, and FIG. 7 is an operational waveform diagram of the main part thereof. Below is a summary of the configuration shown in Figure 6 and the operation of its main parts.
This will be explained with reference to the figure. In FIG. 6, the timing clock generation circuit 19 inputs a clock to each T terminal of D-type flip-flops (FF) 61 and 62 connected in cascade.
By the combination of these Q and outputs, various timing clocks, τ ₁ which is inputted to the clock terminal of the flip-flop in the envelope control circuit 17 via the AND circuit 63, are accumulated via the AND circuit 64 and the AND circuit 65. It generates τ ₂ and τ ₃ for read control to be applied to the register 53 and RAM 54 in the calculator 11, respectively, and τ ₄ to be applied to the envelope control circuit 17 and analog multiplexer 24. In the envelope control circuit 17, cascade-connected D-type flip-flops (FF) 31, 32, 3
The attack signal is applied to the D terminal of the first stage FF31 of 3 and 34, the timing clock τ ₁ is applied to each T terminal, AND
The signal is provided by the circuit 37 in synchronization with the channel time division signal from the channel decoder 21. These FF31 to 34 are delay circuits for initial setting, and the Q output of FF31 and the output of FF33 are input to an AND circuit 38, and the output is input to an OR circuit 4.
0 to the R terminal of flip-flop (FF) 35, and connect the Q output of FF33 and the output of FF34.
Insert it into the S terminal of FF35 through the AND circuit 39,
AND circuit 44 that synchronizes the Q output with the channel
The gate circuit 52 of the accumulator 11 is turned on via the OR circuit 16. On the other hand, carry signals C1 and C2 for determining the attack time and decay time are input from the register 53 of the accumulator circuit 11, and the signal C1 is input to the AND circuit 43,
42 performs timing control and channel synchronization and inputs it to the S terminal of a flip-flop (FF) 36, its Q output is channel synchronized through an AND circuit 45, and its output is inputted to the attack decay coefficient memory 13 via an OR circuit 15. Switch the attack coefficient to the decay coefficient. Furthermore, FF
The reset of FF36 is performed simultaneously in parallel with FF35. Signal C2 is connected to AND circuit 43 and AND circuit 41
This performs timing control and channel synchronization, and is reset by inputting it to the R terminal of the FF 35 via the OR circuit 40, and turns off the gate circuit 52 of the accumulator 11. 7a to 7g are time charts showing the operation of essential parts of the envelope control circuit of FIG. 6. As mentioned above, when the attack signal shown in FIG. Next, in one cycle, the output of the AND circuit 39 generates a set pulse as shown in c in the same figure.
Set FF35. During this reset of FF 35, the contents of channel CH1 of accumulator 11 are cleared, and the next set pulse causes the Q output of FF 35, and therefore the output of OR circuit 16, to go to "H" level. The gate circuit 52 is controlled to be turned on. This causes the accumulator 11 to start calculation. The operation of the signals C1 and C2 will be explained below with reference to the detailed circuit of the accumulator 11. In the accumulator 11, an adder 51, a gate circuit 52, a register 53, and a memory circuit (RAM) 54 are connected in a loop, and the attack decay coefficient memory 13 is connected in response to an address signal from an address counter 20.
The attack coefficient corresponding to this signal is added to the adder 5.
1 is output. The output data of the adder 51 passes through the gate circuit 52 due to the "H" level of the output of the above-mentioned OR circuit 16, and is transferred to the register 53 and the RAM 5.
By controlling the reading of 4 by timing clocks τ ₂ and τ ₃ , the loop is circulated and the accumulation corresponding to, for example, FIG. 4 is performed. The completion of the attack calculation can be known by carrying the C1 signal of the register 53. Figure 7d shows that the attack ends at the MSB bit during the accumulation of the attack calculation, that is, the bit C1-1 immediately before the C1 signal, causing a carry of the C1 signal in the register 53 as shown in Figure 7e. enter. That is, the output of the aforementioned OR circuit 15 is input into the attack decay coefficient memory 13, and the attack coefficient is switched to the decay coefficient. At the same time C
The output of the 1 signal is applied to the EX-OR circuit 22 to invert the output signal of the envelope waveform table 14 to form a decay waveform. When the decay is completed, the C2 signal of the register 53 shown in FIG.
The accumulation is stopped by the output of 6, and the envelope waveform shown in g in the figure is obtained. Further, if there is an attack input again during the attack and decay, it is reset, the accumulator 11 is cleared, and the accumulation starts again. The upper 5 bits of the accumulation results, excluding signals C1 and C2, are input to the envelope waveform table (RAM) 14 as addresses corresponding to the 32 words mentioned above, and the lower 3 bits are discarded. The envelope waveform data passes through the EX-OR circuit 22, is inverted at Decay as described above, and is converted into an analog quantity through the D/A converter 23. However, since the signal up to this point has been a time-division signal, it must be divided for each channel.
Analog multiplexer 24 including AND gates
This time division signal is sent to each channel CH1~ by timing clock _τ4 based on the channel address.
Assign to CH16. The distributed analog data is held in a sample hold circuit 25 and converted into DC data. FIG. 8 shows a detailed circuit example of the accumulator 11 shown in FIG. In the same figure, the values read from the attack decay coefficient memory 13 are added by an adder 51, and when the OR circuit 16 in FIG. 6, which is one input of the gate circuit 52, is at the "H" level,
The 10-bit data from adder 51 is stored in register 53 by timing clock τ ₂ . This output is then input to a 16 word x 10 bit RAM 54 and written at the timing clock _τ3 . When the writing is completed, the address counter 20 increments by one, and the next channel is calculated in the same way. At this time, the RAM 54 outputs the immediately previous value. This immediately previous value is input to the adder 51 and added to the coefficient again. Then, the same operation as the above-mentioned cycle is repeated, and the cumulative result is stored in the RAM 54. As described above, the address information of the envelope waveform table 14 uses 5 bits obtained by removing the signals C1, C2 and the lower 3 bits from the 10 bits. That is, 5 bits are used as the address of 32 words of the envelope table 14. As explained above, according to the present invention, coefficients related to attack time and decay time are stored in an attack decay coefficient storage circuit, and attack and decay are accumulated from the coefficients by an accumulator. The attack signal from the accumulator starts the accumulation of the accumulator, the attack end signal switches the coefficient of the attack decay coefficient storage circuit to Decay, and the output signal of the envelope waveform storage circuit is inverted, and the decay end signal causes the accumulator to start accumulating. This controls the calculation to stop. In this configuration, as illustrated in Tables 1 and 2 above, attack and decay waveforms at arbitrary times can be obtained using the coefficient A _AD related to the attack time and decay time, and the envelope waveform storage circuit Since the waveforms are stored and only need to be inverted in Decay, a large number of envelope waveforms can be obtained with a small amount of storage capacity. Furthermore, if the number of words is large, the quantization steps can be made sufficiently dense, and the configuration is much simpler than the envelope generation circuit that uses charging and discharging of a conventional analog time constant circuit. envelope waveform can be realized. As shown in FIG. 6, the configuration is suitable for large-scale integrated circuits (LSI), so a significant reduction in price is expected. In the embodiment, the case of a rhythm generator is illustrated, but it is clear that it can be applied to the sound generation mechanism of the digital organ shown in Fig. 1. In this case, a key assigner can be used, so conventionally a gate circuit is required for each key. Since it is only necessary to prepare as many hot items as there are to be sounded, the configuration can be simplified from this point of view as well, and it is easy to incorporate it into an LSI.

[Brief explanation of the drawing]

1 and 2 are schematic explanatory diagrams showing the configuration of an embodiment of the present invention, FIG. 3 is an explanatory diagram of an embodiment of an envelope generation circuit which is the main part of FIG.
Fig. 5 is a diagram explaining the principle of the present invention, Fig. 6 is a diagram explaining the principle of the present invention.
Detailed circuit examples of the embodiments shown in the figures, FIGS.
FIG. 8 is a detailed circuit example of the main part of FIG. 6. In the figure, 1 is a key switch, 2 is a key assigner, 3 is a tone generation circuit,
4 is an envelope generation circuit, 5 is an audio device, 6 is a select switch, 7 is a rhythm pattern generator,
8 is a sound source, 11 is an accumulator, 13 is an attack decay coefficient memory, 14 is an envelope waveform table, 15 and 16 are OR circuits, 17 is an envelope control circuit, 19 is a timing clock generation circuit,
20 is an address counter, 21 is a channel decoder, 22 is an EX-OR circuit, 23 is a D/A converter, 24 is an analog multiplexer, and 25 is a sample and hold circuit.

Claims (1)

[Claims for Utility Model Registration] A timing generation circuit 19 that generates timing pulses, an address counter 20 driven by the timing generation circuit, and a coefficient that controls the attack decay time by the address pulse of the address counter. an attack decay coefficient memory 13 from which the attack decay coefficient memory 13 is read; an adder for adding the attack decay coefficient from the attack decay coefficient memory 13 and a value read from the storage circuit; and an adder for storing the addition result and reading it back to the addition circuit. and outputs a cumulative output signal of the attack decay coefficient from the adder in response to a timing pulse of the timing generating circuit and an address pulse of the address counter, and outputs a cumulative output signal of the attack decay coefficient from the adder, and also outputs a cumulative output signal of the attack decay coefficient to a predetermined value. an accumulator 11 which detects that the number of attacks has increased and outputs each end signal of the attack decay; an envelope control circuit 17 which uses a coefficient as an attack coefficient when it is an attack and a decay coefficient when it has a decay; an envelope waveform table that stores the amplitude of an envelope waveform having a logarithmic curve and reads it out using the cumulative output signal; and the envelope waveform. An EX-OR circuit 22 that inverts or non-inverts the output signal of the table, a D/A converter 23 that converts the output signal of the EX-OR circuit 22 into an analog waveform, and an output signal of the address counter 20. The accumulator includes a channel decoder 21 that outputs a time division multiplexed signal corresponding to each channel, and an analog multiplexer 24 that time divisions and distributes the analog output of the D/A converter to each corresponding channel. Using the above time division multiplexed signal,
After time-division operation is performed on each channel and an envelope waveform corresponding to the attack of each channel is formed using the address from the accumulator 11, the decay period output signal from the accumulator 11 is used to perform the attack waveform.
The decay coefficient memory 13 is read out as a decay coefficient, and the envelope waveform table 14
EX-OR the envelope waveform data from
The circuit 22 inverts the waveform to form a decay waveform, and in response to the decay end signal from the accumulator 11, the envelope control circuit 17 terminates the accumulation to form all the envelope waveforms, and then for each corresponding channel. The electronic musical instrument is characterized in that the channel decoder 21 obtains a time-division multiplexed signal for each channel from the output signal of the address counter 20, and the analog multiplexer 24 divides and outputs the time-division multiplexed signal. .