JPH034947Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a matrix display type digital watch.

In recent years, digital clocks using liquid crystal display panels have been widely put into practical use as table clocks, wristwatches, and the like.
This type of digital watch displays hours and minutes by arranging a plurality of digits, for example, four digits, in a date-type numeric pattern. In this case, the display is shown in Figure 1 a, b
In the case of a, it is a 4-digit number, and in the case of b, it is a 3-digit number. In the case of three-digit numbers, the display is biased toward the right side of the display surface, which tends to give the impression that the display is unbalanced.

The present invention was developed in view of these points, and employs a matrix display method that can display arbitrary characters and characters.In the case of a three-digit number as mentioned above, it is distinguished and displayed as shown in Figure 1. As shown in c, the entire displayed numerals are moved slightly to the left so that the displayed numerals are located in the center of the display surface. Note that, for convenience of comparison, Figure c is displayed in a 7-segment numeric pattern in the form of a Japanese letter, similar to Figures A and B, but the display pattern is not limited to this.

An embodiment of the present invention will be described below with reference to FIG. In the figure, the CPU is a central processing unit that includes a crystal oscillator 1, includes a clock function circuit that divides and counts the reference frequency signal generated by the crystal oscillator 1, and generates time signals for hours and minutes, and also performs various processing. Contains necessary registers, arithmetic circuits, control circuits, etc. KB is a keyboard that inputs time adjustment signals etc. to this CPU, and RAM is a random access memory (rewritable memory) to which hour and minute time signals are input from the CPU via data line 2. It stores minute and colon information, and can consist of one digit of 8×8 bits. This RAM is controlled, such as address designation, by a control signal output from a control line 3. That is, the address signal outputted from the CPU through the address line 4 and the control signal from the control line 3 are applied to the AND gate 5, and when the control signal is present, the address signal is outputted through this gate 5 and the OR gate 6.
Specify the storage address of the time data signal that is added to the RAM and input at the same time, and time information is written to this address. SR is a parallel-to-serial signal conversion circuit that converts a parallel time-related signal output from RAM into a serial signal, and FF is a time signal converter that converts a time signal output from a clock function circuit for generating a time signal in the CPU into a serial signal.
This is a flip-flop circuit for determining the number of digits, that is, from 1 o'clock to 9 o'clock, and outputs it.For example, it is set by the time signal of 1:00 obtained from the CPU, This can be realized using a general timer configuration that is reset by the time signal. The set output in this case is applied to the AND gate 7 together with the time signal from the parallel-to-serial signal conversion circuit SR. REG1 is a 4-bit first shift register to which the output of AND gate 7 is added, and 8 is a first shift register REG.
The AND gate REG2, which has two inputs, the output of the AND gate 8 and the output of the flip-flop circuit FF, is a second shift register to which the output of the AND gate 8 is input via the OR gate 9, and 5-digit numerical information is stored. It will be done. That is, the first shift register REG
1 serves as a delay circuit for the second shift register REG2. Reference numeral 10 denotes an AND gate having two inputs: an inverted signal of the flip-flop circuit FF output signal and an output of the parallel-to-serial signal conversion circuit SR; the output thereof is inputted through the OR gate 9 to the second shift register REG2.
BUF is a 1-line buffer circuit that temporarily stores and holds the contents of the second shift register REG2;
The LCD is a matrix display type liquid crystal panel in which minute time information is added to its Y electrode when held in this one-line buffer circuit BUF, and REG3 is a third shift register that selects the X electrode of the liquid crystal panel LCD. operates to designate the address of the RAM by a counter that supplies a clock signal to the buffer circuit BUF and the third shift register REG3 to shift drive them. That is,
The address signal from the counter C is input to the AND gate 11 together with an inverted signal of the control signal from the CPU, which is opened, and further input to the RAM via the OR gate 6. That is, when the control signal is not present, the time information at the address specified by the counter C is read out and output to the parallel-to-serial signal conversion circuit SR.

First, if the time generated in the CPU is 10 o'clock or
A case will be explained in which there are 4 digits including the 12 o'clock information, that is, the minute information. This time signal is written to a predetermined location in the RAM by outputting a control signal. At this time, since the flip-flop circuit FF does not operate, the AND gate 7 is in a closed state and the other AND gate 10 is in an open state. Therefore, the memory contents of the address specified by counter C are:
Parallel-serial signal conversion circuit SR output from RAM
added to. The parallel-to-serial converted signal is directly applied to the second shift register REG2 through an AND gate 10 and an OR gate 9. This signal introduction is repeated five times, including the colons placed between the hours and minutes. As a result, the second shift register REG2 is filled with time information, and this time information is then transferred to the 1-line buffer circuit.
Transferred to BUF. As a result, the time information signal is applied to the Y-axis electrode of the matrix display liquid crystal panel LCD. On the other hand, the above 1-line buffer circuit
At the same time as the time information is transferred to BUF, the contents of counter C are incremented by 1, and the third shift register REG
Step 3 to obtain the signal applied to the X-axis electrode of the liquid crystal panel LCD. In this way, counter C
As the content increases, the time information signal read from the RAM is sequentially applied to the Y-axis electrode of the liquid crystal panel LCD and displayed between it and the selected X-axis electrode.

Next, the time that occurred in the CPU is 1 to 9.
If the time is 3 digits, the flip-flop circuit
FF operates, closes the AND gate 10, and opens the other AND gate 7. Therefore, from the CPU
The time information signal input and stored in the RAM is converted into a serial signal by the parallel-to-serial signal conversion circuit SR, and then input to the first shift register REG1 via the AND gate 7. That is, in this case,
The first and second shift registers REG1 and REG2 are connected, and as a result, the number of shifts of the second shift register REG2 is equal to that of the first shift register.
This means that the number is decreased by the bit of REG1, that is, 4 bits, and the generation timing of the time numerical data in the horizontal direction is delayed by 4 bits. Therefore, the displayed content at this time is shifted to the left by 4 bits. Therefore, this three-digit time information signal shifted to the left is applied to the liquid crystal panel LCD via the buffer circuit BUF.
The display screen is moved slightly to the left, and the time is displayed approximately in the center of the display screen. Note that this number of bits is the optimal number for positioning it approximately at the center of the display screen when one digit is 8 x 8 bits as in this example, and it is the number of bits that make up one digit or the total number of digits. can be changed arbitrarily.

As described above, when displaying the time in a matrix, the matrix display type digital watch of the present invention determines the number of digits of display information and selects one number from a specific number of digits.
When the number of digits is small, the entire display is moved slightly to the left and positioned approximately in the center of the display surface, eliminating the drawback of conventional displays that were biased toward the right and gave an unbalanced impression. can do.

[Brief explanation of the drawing]

FIGS. 1a, b, and c are front views showing the time display state, and FIG. 2 is a block diagram of an embodiment of the present invention. CPU...Central processing unit, RAM...Random access memory, KB...Keyboard, LCD...Liquid crystal display panel, FF...Flip-flop circuit for determining number of digits, C...Counter.

Claims (1)

[Scope of claim for utility model registration] Equipped with clock circuit means for generating time signals
A central processing unit such as a CPU, a storage circuit such as a RAM that stores the time signal from the clock circuit means as time numerical information, and a time numerical value that receives the time numerical information of the storage circuit for each horizontal component of the matrix display. In a digital clock consisting of a display device such as a matrix display type LCD that displays the time, if the time signal obtained from the clock circuit means of the central processing unit is 10 o'clock or more, it is determined that the displayed time has a specific number of digits. A digit number discrimination circuit such as an FF that outputs a first digit number signal indicating that the display signal is less than 10 o'clock and a second digit number signal that indicates that the display signal is one digit smaller than the specific digit number. When the second digit number signal is received from the digit number determination circuit, the time numeric information is moved to the left of the display screen by approximately 1/2 of the display width of one digit. A delay circuit such as a shift register is added to delay the timing of transmitting the horizontal component to the display device by a specific time from the reference timing when the first digit number signal is received from the digit number discrimination circuit, A matrix display type digital watch, characterized in that the time display is located approximately at the center of the time display surface.