JPH0349593U - - Google Patents

Info

Publication number
JPH0349593U
JPH0349593U JP11038989U JP11038989U JPH0349593U JP H0349593 U JPH0349593 U JP H0349593U JP 11038989 U JP11038989 U JP 11038989U JP 11038989 U JP11038989 U JP 11038989U JP H0349593 U JPH0349593 U JP H0349593U
Authority
JP
Japan
Prior art keywords
window
screen
display
memory
showing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11038989U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11038989U priority Critical patent/JPH0349593U/ja
Publication of JPH0349593U publication Critical patent/JPH0349593U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面は本考案の一実施例を説明するためのもの
で、このうち第1図は表示制御装置の回路構成の
概要を示すブロツク図、第2図はRAMにおける
ウインドウ画面用のデータを格納する領域を表わ
した説明図、第3図はデイスプレイの全画面を示
す平面図、第4図はデイスプレイに第1のウイン
ドウ表示された状態を示す平面図、第5図はデイ
スプレイに第2のウインドウが表示された状態を
示す平面図、第6図はデイスプレイに第3のウイ
ンドウが表示された状態を示す平面図、第7図は
キーボードの要部を示す平面図、第8図は表示制
御装置の動作の流れを示す流れ図、第9図はデイ
スプレイにメイン画面データが表示された状態を
示す平面図、第10図はデイスプレイに第1のウ
インドウが表示された状態の平面図である。 11……CPU、13……ROM、14……R
AM、15……キーボード、17……デイスプレ
イ、21……メイン画面データの退避エリア、2
2……第1のウインドウ用エリア、23……第2
のウインドウ用エリア、24……第3のウインド
ウ用エリア、31……表示領域、32……第1の
ウインドウ、33……第2のウインドウ、34…
…第3のウインドウ。
The drawings are for explaining one embodiment of the present invention. Among them, Fig. 1 is a block diagram showing an overview of the circuit configuration of the display control device, and Fig. 2 shows an area in RAM for storing data for a window screen. Fig. 3 is a plan view showing the entire screen of the display, Fig. 4 is a plan view showing the first window displayed on the display, and Fig. 5 is a plan view showing the second window displayed on the display. 6 is a plan view showing the third window displayed on the display, FIG. 7 is a plan view showing the main parts of the keyboard, and FIG. 8 is the operation of the display control device. FIG. 9 is a plan view showing the main screen data displayed on the display, and FIG. 10 is a plan view showing the first window displayed on the display. 11...CPU, 13...ROM, 14...R
AM, 15...Keyboard, 17...Display, 21...Main screen data evacuation area, 2
2...First window area, 23...Second window area
window area, 24... third window area, 31... display area, 32... first window, 33... second window, 34...
...Third window.

Claims (1)

【実用新案登録請求の範囲】 デイスプレイに表示する1画面に対応して用意
されたメイン画面用メモリと、 前記1画面よりも小さな1または複数のウイン
ドウ画面に対応して予め用意されたウインドウ画
面用メモリと、 ウインドウ画面を選択するためのウインドウ画
面選択手段 とを具備することを特徴とする表示制御装置。
[Scope of claim for utility model registration] Main screen memory prepared for one screen to be displayed on a display, and window screen memory prepared in advance for one or more window screens smaller than the one screen. A display control device comprising: a memory; and window screen selection means for selecting a window screen.
JP11038989U 1989-09-22 1989-09-22 Pending JPH0349593U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11038989U JPH0349593U (en) 1989-09-22 1989-09-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11038989U JPH0349593U (en) 1989-09-22 1989-09-22

Publications (1)

Publication Number Publication Date
JPH0349593U true JPH0349593U (en) 1991-05-15

Family

ID=31658924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11038989U Pending JPH0349593U (en) 1989-09-22 1989-09-22

Country Status (1)

Country Link
JP (1) JPH0349593U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05150929A (en) * 1991-11-30 1993-06-18 Sony Corp Display method
JP2009005404A (en) * 2008-09-08 2009-01-08 Yamaha Corp Mixer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05150929A (en) * 1991-11-30 1993-06-18 Sony Corp Display method
JP2009005404A (en) * 2008-09-08 2009-01-08 Yamaha Corp Mixer system

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