JPH0349699U - - Google Patents

Info

Publication number
JPH0349699U
JPH0349699U JP11023789U JP11023789U JPH0349699U JP H0349699 U JPH0349699 U JP H0349699U JP 11023789 U JP11023789 U JP 11023789U JP 11023789 U JP11023789 U JP 11023789U JP H0349699 U JPH0349699 U JP H0349699U
Authority
JP
Japan
Prior art keywords
shift
bits
register
signal line
shift clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11023789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11023789U priority Critical patent/JPH0349699U/ja
Publication of JPH0349699U publication Critical patent/JPH0349699U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の実施例を示す回路図、第２図
は第１図に示された回路の動作を示すタイミング
図である。 １，２……シフトレジスタ、３……Ｄ型フリツ
プフロツプ、４……パルス発生回路、５……計数
回路、６……Ｄ型フリツプフロツプ、７……立ち
上がり検出回路、８……立ち下がり検出回路、９
，１０……ＡＮＤゲート。 FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of the circuit shown in FIG. 1, 2...Shift register, 3...D-type flip-flop, 4...Pulse generation circuit, 5...Counting circuit, 6...D-type flip-flop, 7...Rise detection circuit, 8...Fall detection circuit, 9
,10...AND gate.

Claims (1)

【実用新案登録請求の範囲】 (1) 各々任意のビツト数からなる複数のシフト
レジスタと、 前記シフトレジスタの各々に独立して設けられ
たシフトクロツク信号線と、 クロツク信号に基ずいて、前記シフトレジスタ
の各々のシフトクロツク信号線にそのビツト数だ
けシフトクロツクパルスを順番に供給するシフト
クロツクパルス発生回路と、 を備え、前記各シフトレジスタの入力を共通にに
接続し、且つ、各シフトレジスタの出力を論理和
接続したことを特徴とするシフトレジスタ。 (2) 前記複数のシフトレジスタは同一ビツト数
で構成されたことを特徴とする請求項第１項記載
のシフトレジスタ。[Claims for Utility Model Registration] (1) A plurality of shift registers each having an arbitrary number of bits; a shift clock signal line provided independently for each of the shift registers; a shift clock pulse generation circuit that sequentially supplies shift clock pulses corresponding to the number of bits to each shift clock signal line of each register; the inputs of each shift register are connected in common; A shift register characterized in that the outputs of are logically connected. (2) The shift register according to claim 1, wherein the plurality of shift registers are configured with the same number of bits.
JP11023789U 1989-09-19 1989-09-19 Pending JPH0349699U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11023789U JPH0349699U (en) 1989-09-19 1989-09-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11023789U JPH0349699U (en) 1989-09-19 1989-09-19

Publications (1)

Publication Number Publication Date
JPH0349699U true JPH0349699U (en) 1991-05-15

Family

ID=31658785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11023789U Pending JPH0349699U (en) 1989-09-19 1989-09-19

Country Status (1)

Country Link
JP (1) JPH0349699U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013206492A (en) * 2012-03-27 2013-10-07 Toshiba Corp Semiconductor device and driving method thereof
JP2014164788A (en) * 2013-02-27 2014-09-08 Casio Comput Co Ltd Semiconductor storage device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5291339A (en) * 1976-01-27 1977-08-01 Nec Corp Controlling shift register
JPS60142732A (en) * 1983-12-29 1985-07-27 Matsushita Electric Ind Co Ltd shift register circuit
JPS6293728A (en) * 1985-10-18 1987-04-30 Fujitsu Ltd Fifo memory system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5291339A (en) * 1976-01-27 1977-08-01 Nec Corp Controlling shift register
JPS60142732A (en) * 1983-12-29 1985-07-27 Matsushita Electric Ind Co Ltd shift register circuit
JPS6293728A (en) * 1985-10-18 1987-04-30 Fujitsu Ltd Fifo memory system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013206492A (en) * 2012-03-27 2013-10-07 Toshiba Corp Semiconductor device and driving method thereof
US8908446B2 (en) 2012-03-27 2014-12-09 Kabushiki Kaisha Toshiba Semiconductor device and method of driving thereof
JP2014164788A (en) * 2013-02-27 2014-09-08 Casio Comput Co Ltd Semiconductor storage device

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