JPH035115B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color signal circuit for a PAL color television receiver.

In the PAL system, as is well known, the color subcarrier is orthogonally modulated by two color difference signals, one of which (R-
A color subcarrier suppressed carrier color signal that inverts only the modulation axis on the Y) side by 180 degrees every line and a color burst signal that swings between specific phases in synchronization with the inversion of the R-Y modulation axis are transmitted. It's getting old. Therefore, on the receiver side, the color subcarrier from the color subcarrier generator or the carrier color signal output from the addition/subtraction circuit is inverted line by line and supplied to the R-Y color demodulator. There is a need to.

For this reason, the supply line of the color subcarrier or carrier color signal to the color demodulator on the R-Y side is equipped with a so-called PAL switch for switching the phase by 180 degrees for each line. is controlled to the correct switching (inversion) mode by phase comparison between the color subcarrier passing through it (or the color bust signal in the carrier color signal) and the color burst signal (or color subcarrier) not passing through it. It is becoming more and more like this.

On the other hand, a so-called color killer circuit is installed inside a color receiver, and normally this killer circuit detects the presence or absence of a color burst signal or loss of color synchronization and controls the on/off of the color amplification circuit. It's summery.

Therefore, it would be better to independently provide a color burst phase comparison circuit used to control the inversion mode of such a PAL switch, a color burst detection circuit used for color killer operation, etc. The entire color signal processing circuit including these cannot be configured efficiently, and this is particularly inconvenient when integrating the color signal processing circuit into a single chip IC. because,
When converting to IC, share the circuit as much as possible,
This is because it is desirable to reduce the number of external pins.

Therefore, the present invention aims to reduce the number of circuit elements and external pins by sharing the related circuits of the PAL switch circuit and the color killer circuit, thereby making it possible to reduce the number of circuit elements and the number of external pins. This paper proposes a color signal circuit for the machine.

The present invention will be described in detail below with reference to embodiments shown in the drawings.

In FIG. 1, reference numeral 1 denotes a color amplifier that amplifies a composite color signal (consisting of a carrier color signal and a color burst) applied through a bandpass circuit, and usually uses manual gain adjustment means or an ACC.
(Automatic Color Control) It has a function that automatically changes the gain depending on the signal. 2 is 1H (1
horizontal period) delay line, 4 is by the 1H delay line 2 mentioned above.
Adder 5 adds the 1H delayed composite color signal and the non-delayed composite color signal provided through the straight line 3a, and 5 is the adder that adds the 1H delayed composite color signal and the non-delayed composite color signal provided through the straight line 3b. This is a subtracter that subtracts the non-delayed composite color signal. For example, if the composite color signal has the relationship shown in FIG. 2A, the adder 4
The output of the subtractor 5 is shown in FIG. 2B, and the output of the subtractor 5 is shown in FIG. 2C. 6, 7, 8 are B-Y demodulator, G-
They are a Y demodulator and an RY demodulator. 9 is 4.433618M
It is a voltage-controlled oscillator that generates a Hz color subcarrier, and its output passes through an amplifier circuit 10 and a phase shifter 11 to a B-Y demodulator 6 and a R-Y demodulator 8, each with a certain phase difference (generally is given as a 90° difference) and is also given to the phase comparator 13 of the PLL type color locked loop. This phase comparator 13 compares the phase of the color burst of a constant phase extracted by the color burst gate 12 from the output of the adder 4 [FIG. The voltage is then applied to the voltage controlled oscillator 9 as a control voltage. A sweeper circuit 15 is provided to ensure color synchronization by the output of the phase comparator 13, and is designed to output a stepwise sweep voltage waveform. Reference numeral 16 denotes a means for applying a pulse voltage of a constant frequency (for example, fH/32 when fH is the color burst repetition frequency, that is, the horizontal frequency) to make the output of the sweeper circuit 15 stepwise. Reference numeral 17 denotes a color killer circuit provided to receive the color burst period outputs of the G-Y demodulator 7 and the R-Y demodulator 8 and to stop the function of the color amplifier 1 when receiving monochrome broadcasting or abnormally receiving color broadcasting. However, the output of this color killer signal generation circuit 17 is simultaneously supplied to the sweeper circuit 15, and the sweeper circuit 15 is stopped when color broadcasting is normally received (for example, when color synchronization is achieved), and when it is not. Sometimes it works. Therefore,
As will be described later, this color killer signal generation circuit 17 detects an abnormality in the R-Y demodulator and G-Y demodulator outputs when the PAL switch is not normally switched, and when the PAL switch is normally switched. functions to detect the normal output of each of the demodulators 7 and 8 and to control the operation of the PLL type color synchronization circuit. 24, even when the killer output to the color amplifier 1 should be disabled and the color amplifier 1 should be stopped during the color burst period or the horizontal retrace period including the color burst by the pulse _P2 , at least the color burst period is a killer nullification method to prevent the system from stopping. 20 is a PAL switch, which connects the output of the subtracter 5 to the output via the 180° phase shifter 18 and the direct path 1.
9 is alternately taken out every 1H and supplied to the R-Y demodulator 8, and the switching operation is performed by the output of the flip-flop 21. Flip-flop 21 is driven by a horizontal frequency trigger _pulse P ₃ which is applied to flip-flop 21 through switch 22 . The switch 22 is in the on state during normal reception, but when the lock of the PLL color synchronization circuit has not been locked, the switch 22 is turned off once within a predetermined period and the trigger pulse _P3 is turned off to 1.
Disable one. Such driving of the switch 22 is performed by a extraction drive means 23 connected to the sweeper circuit 15. When the PLL color synchronization is locked, the extraction drive means 23 is inactive and the switch 22 therefore remains closed. In the above description, it should be understood that when one trigger pulse _P3 is disabled by the switch 22, the reversal operation of the flip-flop 21 and therefore the switching mode of the PAL switch 20 will be reversed. It is.

The operation of the circuit shown in FIG. 1 will be further explained with reference to specific examples shown in FIG. 3 and subsequent figures. In FIG. 3 showing the voltage controlled oscillator 9, the operation will now be considered assuming that points a and b of the oscillation loop are open and a signal ei is input from point b. First, a vibrator 25 based on LiTaO ₃
Since the impedance of [hereinafter referred to as "LiTa resonator"] becomes 0 at the resonant frequency (4.433618MHz), R _B /R _B + R ₃₃ ei is input to the base of one transistor T ₂₅ that forms the differential pair. . The other transistor of the differential pair T ₂₄
Since ei is input as is to the base of , the differential pair transistors T ₂₄ and T ₂₅ amplify the input difference voltage (1−R _B /R _B +R ₃₃ )ei. Here the collector outputs of T ₂₄ and T ₂₅ are
Let e ₂₄ and e ₂₅ respectively, e ₂₄ and e ₂₅ have a phase difference of 180°. e ₂₄ and e ₂₅ are input to emitter follower transistors T ₃ and T ₄ , respectively, while resistors R ₁₂ and
Since R ₁₃ and R ₁₈ are selected to satisfy the relationship R ₁₂ + R ₁₃ = R ₁₈ , there is no residual signal at point da, and no signal is input to transistor T ₁₇ .
The signal _e24 passes through the emitter follower transistor _T3 and enters the phase shift circuit 26 composed of R _A and C _A from point e. The signal voltages applied to both ends of R _A and C _A are respectively
Assuming e _R and e _C , if the impedances of R _A and C _A are equal, there will be a phase difference of 90°. These e _R and e _C are added to differential pairs T ₁₄ , T ₁₅ , T ₁₆ , and T ₁₇ , respectively. differential pair
mer reversed by 180° by T ₁₄ , T ₁₅ , T ₁₆ , T ₁₇ ,
nec (m, n are constants) are added at point f and K(e _R +e _C )
(K is a constant) and is output to point a via emitter follower transistors T ₂₁ and T ₂₃ . terminal a
When and b are short-circuited, it is added to ei at point b, and the same operation occurs and oscillation occurs. Figure 4 shows a vector diagram.

Next, FIG. 5 shows the phase comparator 13 and the burst gate 12, which are integrally formed as a double-balanced differential circuit, and one of the lower differential pairs T ₁₃₀ and T ₁₃₁ . The base of T ₁₃₁ is fixedly biased by V ₀₁ , while the base of T ₁₃₀ is provided with a composite color signal from color amplifier 1. Since the constant current source transistor T ₁₃₂ is supplied with the burst gate pulse P ₁ to its base and is conductive only during the burst gate period, only the color burst is extracted from the decoded color signal and the lower stage differential pair T ₁₃₀ , T ₁₃₁ collector, upper differential pair
It is supplied to the emitters of T ₁₂₆ , T ₁₂₇ , T ₁₂₈ , and T ₁₂₉ . Among the upper differential pairs T ₁₂₆ , T ₁₂₇ , T ₁₂₈ , T ₁₂₉ ,
A fixed bias Vo ₂ is given to the bases of T ₁₂₇ and T ₁₂₈ , and the color subcarrier CW from the voltage controlled oscillator 9 is given to the bases of T ₁₂₆ and T ₁₂₉ , so that the color burst and the color subcarrier are connected to each other. A phase comparison (by multiplication) is performed. As a result, the first output is T ₁₂₆ .
A second output appears at point g where the collectors of T ₁₂₈ are commonly connected, and a second output appears at point h where the collectors of T ₁₂₇ and T ₁₂₉ are commonly connected. The first and second outputs are in opposite phase to each other,
The first output is transistors T ₁₂₀ , T ₁₂₁ , T ₁₂₂ and resistors
Transistors _{T 133 ,} T _{134 ,} T _{135 ,}
The current mirror circuit 28 composed of resistors R ₁₅₃ , R ₁₅₄ , and R ₁₅₅ appears at point i as the collector output of transistor T ₁₃₅ . On the other hand, the second output consists of transistors T ₁₂₃ , T ₁₂₄ , T ₁₂₅ and resistors R ₁₄₉ , R ₁₅₀ , R ₁₅₁
It is output to point i as the output of the transistor T ₁₂₄ through the current mirror circuit 29 composed of the following.

Figure 6 shows the switching operation of the transistor due to the color burst and the color subcarrier CW, and the output waveform based on the switching operation.
Taking the case where the CW (FIG. 6B) is shifted by -1/2 fH as an example, the signals of those beat frequencies, that is, the phase comparison output, appear as shown in FIG. 6C. This output signal is transmitted from point i to a double time constant circuit [R _C and C _D in Figure 5 are high frequency filters, R _C and C _C
The voltage is supplied to the voltage controlled oscillator 9 as a control voltage through a low pass filter 14 formed as a low frequency filter. In FIG. 7, the horizontal axis is time and the vertical axis is the control voltage, but curve A simply shows the output of the phase comparator 13, and when no PLL loop is applied,
That is, this is a case where automatic color synchronization is not applied. Now considering the case where automatic color synchronization is applied, since the control voltage is positive during the period _t0 to _t6 , the voltage controlled oscillator 9
The oscillation frequency increases and the beat frequency decreases, while the control voltage is negative during the period _t6 to _t12 , so the beat frequency increases, as shown by curve B in FIG. The control voltage curve B crosses the potential E that stably oscillates at 4.433618 MHz at two points Z ₁ and Z ₂ , but the slope of the above curve is positive Z ₁ point is an unstable point and the slope is negative Z ₂ Since this point is a stable point, when the control voltage reaches point _Z2 , the voltage controlled oscillator 5 is locked to the oscillation frequency of 3.579545 MHz.

By the way, as mentioned earlier, the LiTa resonator 25 is used as the resonator of the voltage controlled oscillator 9;
When such a LiTa resonator is used, it is possible to enjoy the advantage that the price of the resonator is much lower than when a crystal resonator is used. However, the frequency variable range due to the control voltage of a voltage controlled oscillator using a LiTa resonator is as wide as approximately ±7KHz due to the small Q of the LiTa resonator 25, whereas the frequency variable range of a conventional voltage controlled oscillator using a crystal resonator is wide. Range is approximately ±700Hz
This is approximately 10 times higher than that of the previous year. The frequency spectrum of color burst is schematically shown.
They appear at fH intervals around 4.433618MHz, as shown in Figure 8. Of these, only the frequency of 4.433618MHz is required, and since there is a ±fH interval from 4.433618MHz to the adjacent frequency component, even in a voltage-controlled oscillator using a LiTa resonator, the color synchronization circuit is activated by the adjacent frequency component. There will be no malfunction. However, as mentioned above, the frequency variable range of a voltage-controlled oscillator using a LiTa resonator is about 10 times that of one using a crystal resonator, so a voltage-controlled oscillator using a LiTa resonator is used. The retraction range of the PLL loop is approximately 10 times larger. If the frequency pull-in range is wide, there is a problem in that the noise resistance in a weak electric field deteriorates (noise is generally intense in a weak electric field, but the device operates even with this noise). Therefore, we focused on the fact that the oscillation frequency variable range of the voltage controlled oscillator is proportional to the amplitude of the beat signal generated at the output of the phase comparator 13. By passing it through the filter 14, it is sufficiently attenuated (for example, to 1/10) to narrow the frequency pull-in range, and the noise resistance in a weak electric field is improved to the same level as when using a crystal resonator. By the way,
The resistance R _C of the low-pass filter 14 is 390Ω, and R ₁₅₂ is
500Ω, capacitor C _C is 4.7μF, C _D is 10000PF. Furthermore, since the beat signal amplitude is reduced in this way, as shown in FIG.
This results in a problem that the PLL loop does not reach the stable potential E of 4.433618MHz, and therefore does not lock onto 4.433618MHz.In order to solve this problem, a sweeper circuit 15 is provided to control the beat signal and the sweep. A beat signal is generated by superimposing the voltage
To reach a stable potential of 4.433618MHz,
Lock the PLL loop. In this case, the sweep voltage waveform is not a mere sawtooth waveform but a stepped waveform as described later. If the PLL is locked by inputting a continuous wave as a reference signal, a sawtooth waveform will be fine, but if an intermittent signal such as a color burst is used as a reference signal for automatic color synchronization, a sweep voltage waveform is acceptable. Even if you superimpose
This is to solve the problem that PLL color synchronization is not locked. For example, in a PLL using an intermittent signal as a reference signal as shown in Figure 11B, the first
When a simple sawtooth voltage is used as the sweep voltage to be superimposed as shown in Figure ₁₁ ,
However, since the information as a reference signal is intermittent, the phase comparison output of the PLL loop is insufficient and locking is not performed, and the next sawtooth wave falls at point X ₂ . But you can't lock it in the same way. Incidentally, although not particularly shown at the rise of the sawtooth wave, it goes without saying that no lock is applied. Furthermore, in a PLL that uses a continuous signal as a reference signal instead of an intermittent signal, the detection output and therefore the control output are sufficient, but even in this case, there is still the drawback that locking is difficult to achieve by simply superimposing a sawtooth wave voltage. it is,
This is because even if the control voltage reaches the stable potential E at point _Z3 as shown in FIG. 12, there is a high possibility that it will not be locked because the sweep voltage S has fallen.
On the other hand, in this embodiment, the voltage waveform has a step-like shape as shown in FIG. 13 (in the embodiment, only the falling edge is used, so it is sufficient to have a step-like shape only for the falling edge). Since the period sweep voltage does not decrease, the comparative output of the phase comparator 13 (color burst and color subcarrier beat signal) crosses the stable potential E many times during the T period close to the stable potential E as shown in FIG. Receive the opportunity to be locked at Z ₄ , Z ₅ , Z ₆ points. Moreover, in reality, the T period is selected to be long (about 16 times the horizontal period), so the color burst, which is an intermittent signal, is transmitted over multiple lines in one line.
Since the 6H signal is used during the T period, a sufficient control signal can be obtained despite the time constant of the low-pass filter 14, and the stable potential E
The lock will be certain.

Next, the sweeper circuit 15 will be explained with reference to the embodiment shown in FIG.

In Figure 15, if capacitor C _C of low-pass filter 14 (this filter is also shown in Figure 5) is not charged, the potential at point K is
When E ₁ is assumed, the potential at point l becomes E ₁ −Vf (where Vf represents the base-emitter voltage when the transistor is conductive). Since capacitor C _C is not charging, the potential at point m is 0, and transistors T ₂₇ ,
T ₂₉ is cut off. In this case, finding the potential at point n, point k → R ₂₄ → R ₂₇ → R ₃₄ → T ₂₈ → R ₃₅
→A current flows through the earth path, and this current is D ₅ ,
Since it is determined by D ₆ , D ₇ , T ₂₈ , and R ₃₅ and given by i=2Vf/R ₃₅ , the potential E ₂ at point n is E ₂ = E ₁ −i (R ₂₄ + R ₂₇ )=E ₁ −2Vf/R ₃₅ (R ₂₄ + R ₂₇ ). Therefore, it is assumed that the design is made in advance so that E ₂ <E ₁ −Vf. Since E ₂ <E ₁ −Vf, T ₃₄ of the differential pair T ₃₄ and T ₃₅ is turned off and T ₃₅ is turned on. When T ₃₅ is on, current flows through resistor R ₄₁ and causes a voltage drop, turning on transistors T ₃₁ , T ₃₂ , and T ₄₀ . When the transistor T ₄₀ is turned on,
Current flows through the transistor T ₄₀ and the transistor
Since the transistor _T47 is turned on by supplying the base current to the transistor _T47 , the collector potential of the transistor _T47 becomes 0V if the resistance between the collector and emitter is ignored, and no base current flows through the transistor _T30 . Transistor T ₃₀ is cut off. As mentioned above, since the transistor _T31 is in the on state, a charging current flows into the capacitor _CC through the point m. At this time, the transistor T ₃₀ is in the cut-off state as described above, so the current does not flow through the transistor 30. As capacitor C _C is charged, the potential at point m increases, and accordingly, the potential at point n also increases. the transistor
Since the transistor T ₃₂ is also in the on state along with T ₃₁ and T ₄₀ , the potential difference generated across the resistor R ₄₆ increases and the potential at point l also rises, but when it exceeds E ₁ ,
Transistor T ₃₇ is turned off and transistor T ₃₉ is turned on instead, so the potential at point l is clamped to the value of E ₁ +Vf. When the n-point potential becomes higher than the l-point potential, differential pair T ₃₄ and T ₃₅ turn on T ₃₄ .
T ₃₅ is turned off. When T ₃₄ turns on, transistors T ₃₁ , T ₃₂ and T ₄₀ turn off. And by turning off the transistor _T31 , the capacitor
Since charging current no longer flows to C _C , the capacitor
C _C is not charged and moves to discharge. Since the transistor T ₄₀ is turned off, no base current is supplied to the transistor T ₄₇ , and the transistor T ₄₇ is also turned off. For this reason, the base of transistor T ₃₀ is biased through R ₃₉ and the capacitor C _C
The charge is discharged along the path of point m → T ₃₀ → R ₃₆ . By turning off the transistor _T32 , the potential at point l drops to _E1 -Vf. In the above, when T ₃₄ of the differential pair is turned on, transistor T ₃₃ is turned on, and current flows from the power supply +V _CC to ground through resistors R ₄₃ and R ₄₄ and transistor T ₃₃ . This means that when charging the capacitor C _C +V _CC →R ₃₇ →T ₃₁ →
This is to prevent ripples from appearing on the power supply +V _CC by flowing the same amount of current as the current that flowed from point m to capacitor _CC . Capacitor C _C discharges,
When the potential at point n falls below the potential at point l, the above-described charging and discharging are repeated. As far as the above explanation is concerned, the sweep voltage is a mere sawtooth wave as shown in _FIG .
By applying a pulse with a frequency of fH/32 from [see Figure 1], this transistor _Q36 turns on and off, and accordingly, the transistor _T30 turns on and off, changing the potential at point m and the potential at point q. The potential has a staircase waveform as shown in FIG. 13 during the falling period.
That is, since the transistor Q ₃₆ is off at the low level of the pulse from the pulse supply means 16, the transistor T ₃₀ is in the on state [power supply +V _CC →R ₄₉ →
Since the base bias given by the path of the base of R ₃₉ →T ₃₀ is not nullified, it is in the on state], and the charge of the capacitor _C is discharged through the collector and emitter of the transistor T ₃₀ and the resistor R ₃₆ , so that m, q The potential at the point drops. Said fH/
At the high level of the 32 pulse, transistor Q ₃₆ turns on, disabling the base bias of transistor T ₃₀ to 0V, so that transistor T ₃₀
The discharging operation of capacitor C _C stops due to m,
The potential at point q stops dropping. Incidentally, the period of the sweep voltage waveform may be selected to be, for example, 500 to 600 times the horizontal period. As shown in FIG. 1, the color killer signal generation circuit 17 generates a color killer signal based on the color burst period outputs of the R-Y demodulator 8 and the G-Y demodulator 7.

In the color killer signal generation circuit shown in FIG.
Low-pass filter 3 consisting of R ₁₀₁ and capacitor C ₂
Transistor T ₇₆ for emitter follower through 2
and is supplied to the base of a transistor T 77 forming a differential pair for the comparator 33 through a resistor R ₉₅ on _the emitter side of this transistor T ₇₆ . On the other hand, the output of the G-Y demodulator is connected to the resistor from the line 34.
_R108 , emitter follower transistor _T79 via low pass filter 35 consisting of capacitor _C10
The emitter of this transistor _T79 is directly applied to the base of the other transistor _T78 constituting the comparator 33. Here, the DC bias from the demodulator applied to the lines 31 and 34 is the same, and the resistors R ₁₀₁ and R ₁₀₈ and the capacitors C ₂ and C ₁₀ are each selected to have the same value. and the G-Y path are under the same conditions, but since the R-Y demodulator output side is provided to the comparator 33 via the resistor _R95 , this resistor R is higher than the G-Y demodulator output side. It will be added at a lower value by the voltage drop caused by ₉₅ . This voltage drop is approximately 0.3V. The output of the comparator 33 is given to an integrating circuit 37 via a current mirror circuit 36 formed of transistors T ₇₃ , T ₇₄ , T ₇₅ and resistors R ₉₂ , R ₉₃ , R ₉₄ , and is smoothed by the integrating circuit 37 . be done. Such a smoothed output is connected to the differential pair T ₇₀ and T ₇₁ via the emitter follower transistor T ₇₂ (as a supply bias, a fixed potential V ₁ is directly applied to the base of T ₇₀ , and a diode D ₁₀ is applied to the base of T ₇₁ ). Resistance R ₈₇ ,
is applied to the color amplifier 1 shown in FIG _. 1 from the collector of the common-emitter transistor T ₆₉ , while the collector of the common-emitter transistor T ₆₈ is applied to the sweeper circuit. It is supplied to the bases of 15 transistors T ₄₂ and T ₄₃ . The comparator 33 operates only during the burst gate pulse _P1 applied to the base of the constant current source transistor _T83 , and is inactive at other times, so that the R-Y demodulation applied from the lines 31 and 34 Outputs other than the color burst period among the output of the demodulator and the output of the G-Y demodulator have no influence on the color killer operation.

In FIG. 16, if we consider the case where there is no color burst (for example, when receiving a black and white broadcast), the comparator 3
Since the base potential of the third differential pair transistors T ₇₇ and T ₇₈ is selected in advance to be higher than that of T ₇₈ , T ₇₇ is off and T ₇₈ is on. Therefore, no current flows through the current mirror circuit 36, and since the capacitor C _E of the integrating circuit 37 is not charged, u
The potential at the point does not increase. Therefore, in the differential pair transistors T ₇₀ and T ₇₁ on the output side, T ₇₀ is on and T ₇₁ is off. The transistor T ₆₉ is turned on by the on state of the T ₇₀ , and a high level voltage is generated at the first output point O ₁ to stop the color amplifier 1 [However, the signal at the first output point O ₁ is applied through the killer nullifying means 24 Therefore, the color amplifier 1 is not stopped at least during the color burst period. ]. On the other hand, due to the off state of the transistor _T71 , the transistor _T68 is off, and no voltage for stopping the sweeper circuit 15 is generated at the second output point _O2 , so that the sweeper circuit 15 is in an operating state.

Next, if we consider the case where there is a color burst and the reception status is normal (the PAL switch 20 is also normal), the color burst input from the subtracter 5 to the R-Y demodulator 8 can also be seen in Figure 2D. As shown, since it is in phase with the demodulation axis of the R-Y demodulator, the color burst demodulation output of the R-Y demodulator 8 becomes a positive voltage, the potential of the line 31 rises, and the base current of the transistor _T77 also remains constant. or more. On the other hand, G
-Y demodulator 7 was originally an R-Y demodulator and a B-
The demodulated output from the Y demodulator is input and matrixed, and compared to the R-Y demodulator and B-Y demodulator outputs, 3/
However, during normal reception, the color burst demodulation output of the R-Y demodulator is positive, and the color burst demodulation output of the B-Y demodulator is negative. Vessel 8,
The demodulated output matrix of No. 6 is approximately OV, and G
-Y demodulator output system provides only the original DC bias through line 34.
"In such a state, the operations of transistors T ₇₇ and T ₇₈ are reversed, with T ₇₇ turned on and T ₇₈ turned off. When transistor T ₇₇ is turned on, current flows through the current mirror circuit 36 and passes through the point U to the capacitor.
Since a current flows to charge C _E , the potential at point u rises. Due to the rise in potential at point u, the transistor
The base potential of _T72 also increases and the differential pair transistor
T ₇₀ is off and T ₇₁ is on. When T ₇₀ is turned off, no base current is supplied to the transistor T ₆₉ , so that the transistor T ₆₉ is turned off, and no voltage is generated at the first output point O ₁ to stop the operation of the color amplifier 1. Therefore, the color amplifier 1 operates normally. On the other hand, when the transistor T ₇₁ is turned on, the transistor T ₆₈ is also turned on, and a high level voltage is generated at the second output point O ₂ . Since this high level voltage is applied to the bases of the transistors T ₄₂ and T ₄₃ of the sweeper circuit 15, the transistor T 68 is also turned on. ₄₂ and T ₄₃ are turned on to clamp the base potential of transistors T ₃₀ and T ₃₆ to the ground potential, so that transistor T ₃₀ is fixed to OFF, and differential pair T ₃₄ and T ₃₅ are inactive, and the sweeper circuit 15 is turned on. The sweep operation will stop.

However, if you are receiving a color broadcast and the receiving condition is not normal [for example, if the PAL switch 20
If the switching is not normal], the color burst input to the R-Y demodulator 8 has a polarity opposite to that of the demodulation axis of the R-Y demodulator 8, as shown in FIG. The color burst demodulated output of the Y demodulator 8 becomes negative, and the output from the supply line 31 becomes low. At this time, since the phase of the color burst supplied from the adder 4 to the B-Y demodulator 6 remains unchanged, the B-Y
The color burst demodulation output of demodulator 6 remains negative. Therefore, since negative color burst demodulation outputs are given to the G-Y demodulator 7 from both the R-Y demodulator 8 and the B-Y demodulator 6, the color burst demodulation output of the G-Y demodulator 7 is also in the negative direction. A small amount occurs. In such a state, transistors T ₇₇ and T ₇₈
In this operation, _T78 is turned on and _T77 is turned off, and no current flows through the current mirror circuit 36, and the potential at point U does not rise, so the color amplifier 1 is stopped (however, it is not stopped during the color burst period by the killer nullifying means 24). ] However, the sweep circuit 15 performs a sweep operation, and the PLL color synchronization is not locked.

The color killer signal generation circuit shown in Fig. 16 is equipped with an auxiliary circuit 38 that quickly discharges the charge in the capacitor C _E when color synchronization is disturbed to prevent color noise from occurring on the screen. The auxiliary circuit 38 is formed by a differential pair transistors T ₈₁ and T ₈₂ , a constant current source transistor T ₈₄ , a resistor R ₁₀₂ , and a backflow prevention diode D ₁₁ . and,
The R-Y demodulated output and the G-Y demodulated output input to this auxiliary circuit 38 are provided with levels opposite to those input to the comparator 33 described above. That is, the R-Y demodulator output is supplied directly from the emitter of the emitter follower transistor T ₇₆ to the base of the transistor T ₈₂ , while the G-Y demodulator output is supplied from the emitter of the emitter follower transistor T ₇₉ to a voltage drop of 0.3V. Resistance of R ₁₀₀
Since the demodulator output is applied to the base of the transistor _T81 through the comparator 33, it has a magnitude relationship opposite to that of the demodulator output applied to the comparator 33. Constant current source transistor
The burst gate pulse P ₁ is applied to the base of T ₈₄ in common with the constant current source transistor T ₈₃ for the comparator 33, and therefore the auxiliary circuit 3
8 also operates only during the color burst period. Since the base potential of the transistor _T82 is selected to be higher than the base potential of the transistor _T81 , the transistor T82 is turned on and the transistor _T81 is turned off when there is no color burst or when there is a color burst and _{the reception} is normal. Since it is u
It has no effect on the potential at the point. however,
For example, when receiving a color broadcast in a weak electric field, the phase of the color burst tends to be random, but if the color burst is disrupted in this way or the switching mode of the PAL switch 20 is not normal, the R
-Y demodulator 8 produces a negative color burst demodulation output. In such a case, the transistor of comparator 33
Since T ₇₇ is off, capacitor C _E will not be charged, but if you switch from a normal field channel to a weak field channel, or if the PAL switch 20 goes from normal mode to error mode, capacitor C Since the charge charged during normal reception remains in _E for a while, color noise will occur on the screen during that time, but in such a case,
Due to the action of the auxiliary circuit 38, the charge in the capacitor C _E is immediately discharged, so that the color amplifier 1 is stopped and the color noise on the screen disappears immediately. That is, the transistor T ₈₁ of the auxiliary circuit 38 is turned on, and the charge in the capacitor C _E is immediately discharged through the capacitor C _E → diode D ₁₁ → transistor T ₈₁ → constant current source transistor T ₈₄ and resistor R ₁₀₂ → ground. It is from.

FIG. 17 shows a color killer signal generating circuit according to another embodiment. This circuit differs from FIG. 16 in that the line 34 is connected to the B-Y demodulator 6,
while another transistor in parallel with transistor T ₇₉
In addition to adding a transistor T ₈₀ , the G-Y demodulator 7 is connected to the base of the transistor T ₈₀ via a line 39. This circuit is
Suitable for television receivers capable of receiving NTSC broadcasts and PAL broadcasts; when receiving NTSC broadcasts, transistor _T158 connected to point W is turned on, and the base of transistor _T80 is grounded. As a result, the G-Y demodulator output is cut off and the comparator 33 and the auxiliary circuit 38 are operated only by the R-Y demodulator output and the B-Y demodulator output, and the PAL
When receiving broadcasts, the output of the G-Y demodulator is used by turning off the transistor _T158 . Note that line 39 is not equipped with a capacitor for a low-pass filter, but PAL
There is no problem in that case. However, it goes without saying that a capacitor for a low-pass filter may be provided.

As described above, the color killer signal generating circuit 17 keeps the transistors T ₄₂ and T ₄₃ in the off state when the frequency or phase of the color subcarrier generated from the voltage controlled oscillator 9 deviates considerably. Therefore, the sweeper circuit 15 performs the sweep operation described above. On the other hand, if the frequency and phase of the color subcarrier are within a certain range, the transistors T ₄₂ and T ₄₃ are turned on, and the sweeper circuit 15 is fixed in the stopped state, and the color subcarrier is fixed in the stopped state. The synchronous PLL is locked. In the locked state, the output of the phase comparator 13 becomes 0 in DC terms. This is shown in the current waveform in FIG. 18A.

Once the lock is applied, the frequency of the beat signal (beat of the color subcarrier and color burst) that is the output of the phase comparator 13 is so low that it can be regarded as approximately direct current, so the time constant of the low-pass filter 14 becomes large. Emitsuta follower transistor T ₂₇ ,
Since the input impedance of T ₂₉ (FIG. 15) is also large, the gain of the phase comparator 13 is large. In the locked state, as shown in FIG. 18B, a current (shaded area) flows according to the phase and frequency shift, and the voltage generated by this current is applied to the voltage controlled oscillator 9.
It joins [the base of T ₁₉ in Figure 3]. 1st
In Figure 8, the horizontal axis indicates the amount of shift of the color subcarrier,
The vertical axis shows the output of the phase detector.

As mentioned above, if the switching of the PAL switch 20 is not normal, the sweeper circuit 15 continues the sweeping operation due to the action of the color killer signal generation circuit 17.
PLL color synchronization will not be locked, but if there is no way to return the switching to normal, PAL switch 2
0 will never go into normal switching mode. Such a means is achieved by a switch 22 provided in the supply path of the trigger pulse _P3 to the flip-flop 21 in FIG. When the PAL switch 20 is normally switched, the color bursts of each line are aligned upward (in phase with the R-Y demodulation axis) as shown in Fig. 2D.
If the switching is incorrect, the direction will be downward as shown in FIG. 2E. Therefore, when the PLL color synchronization has never been locked, only one trigger pulse (FIG. 19B) is extracted within the stepwise sweep voltage period T (FIG. 19A). Therefore, the trigger pulse is generated during the period T as shown in FIG. 19C.
Each item will be invalidated one by one. And when one is removed, the previous PAL switch 2
It will be readily appreciated that the 0 switching mode is the opposite of the previous switching mode. For this reason R
- The color burst demodulation output of the Y demodulator 8 is the 19th
It will look like Figure D. Then, PLL color synchronization is locked in the upward direction. 1st
In FIG. 9D, part F is a case where the color synchronization is disturbed, so the color burst demodulation output of the R-Y demodulator 8 occurs in both the positive direction and the negative direction.
In such a case, the capacitor C _E is not charged by the auxiliary circuit 38 in the color killer circuit 17 and the sweep operation of the sweeper circuit 15 does not stop, so the PLL color synchronization is not locked, but the J part in FIG. It can be locked. Once locked, the sweeper circuit 15 is stopped and the extraction drive means 23 is also stopped, so the switch 22 remains closed and the trigger pulse _P3 is not extracted, so that the PAL The switch 20 continues to operate in the normal switching mode. In this way
The switching mode of the PAL switch 20 is set to a normal state.

It goes without saying that the extraction of the trigger pulse _P3 may not be performed during the constant potential period T of the stepped sweep voltage, but may be performed during the falling period t of the sweep voltage. It is carried out at T. In the embodiment of FIG. 15, the withdrawal of the trigger pulse P ₃ and thus the forced reversal of the switching mode of the PAL switch 20 occurs during the falling period t.
It has become common practice to do so in

As previously explained in FIG. 15, a pulse of fH/32 to the base of the transistor Q ₃₆ is applied from the pulse supply means 16, and the sweep voltage waveform becomes step-like _.
Transistor with base connected via R ₈₀
T ₄₄ becomes conductive when the transistor T ₃₀ is turned on, ie, when a base bias is applied during the falling period t of the sweep voltage. Therefore, since the emitter of transistor T ₄₅ is coupled to ground, transistor T ₄₅ becomes
Turns on or off depending on its base state. However, one pulse is applied to the base from the second pulse supply means 40 within the period t, and T ₄₅ is in the ON state only during that pulse period. Accordingly, the transistor _T67 is also turned on and the potential at the point X rises to +V _CC , so the switch 22 is turned off and one trigger pulse _P3 is invalidated. In the above, the pulses of the second pulse supply means 40 are sufficient to cover the one trigger pulse. At times other than the pulse period from the second pulse supply means 40, the transistor _T45 is off, so the transistor _T67 is also off, and the
The potential at the point does not rise and the switch 22 is turned on. When PLL color synchronization is applied, a high level is applied from the color killer signal generation circuit 17 to the bases of transistors T ₄₂ and T ₄₃ , and the transistors T ₃₀ and
T ₃₆ is fixed off, and accordingly the base potential of transistor T ₄₄ becomes 0, and the transistor
Since T ₄₄ is fixed off, the transistor T ₄₅ is turned off regardless of whether a pulse is applied from the second pulse supply means 40, and therefore the switch 22 remains on. In FIG. 15 as well, a transistor T ₆₇ and a switch 22 are connected to the connection line 41 of the volume VR for manually adjusting the gain of the color amplifier 1, but when the PLL color synchronization has not occurred, the color amplifier 1 Since the output of the killer signal generation circuit is cut off during the scanning period and the carrier color signal is stopped, the voltage set by the gain adjustment volume VR will be broken as described above when the PLL color synchronization has not been achieved. There is no problem. When PLL color synchronization is applied, the transistor _T67 is cut off, as is clear from the above explanation, so that the voltage set by the gain adjustment volume VR is applied to the color amplifier 1 without being disturbed. In addition, in this way, switch 22
The advantage of using the color gain adjustment volume VR line to control is the switch 22 in the case of an IC.
The terminal pin for extracting the control voltage from inside the IC for control can be shared with the external pin for the color gain adjustment volume VR, so one less terminal pin is required. In FIG. 15, T ₄₄ , T ₄₅ , R ₅₂ , T ₆₇ , 40, etc. form the extraction drive means 23 of FIG. 1.

As described above, in the present invention, by sharing the related circuits of the PAL switch and the color killer circuit, the color signal circuit including each of these circuits can be efficiently configured with a small number of circuit elements.
Since the signal given from the color killer signal generation circuit to the inverting drive means of the switch is supplied through the connection line between the color amplifier and its gain adjustment volume, when integrated into an IC, it is possible to connect the signal to the external terminal pin. It has the advantage of requiring less.

[Brief explanation of drawings]

All drawings relate to the present invention,
Figure 1 is a block diagram of the color signal circuit of a PAL color television, Figure 2 is a signal vector diagram at each point, Figure 3 is a specific circuit diagram of a part of Figure 1, and Figure 4 is a block diagram of the color signal circuit of a PAL color television. 5 is a circuit diagram showing a specific example of a part of the configuration shown in FIG. 1, FIGS. 6 and 7, FIG. 8, FIG. 9, FIG. Figures 12, 13, and 14 are explanatory diagrams of Figures 1 and 5, etc., Figure 15 is a specific circuit diagram of a part of the configuration in Figure 1, and Figure 16 also shows the configuration in Figure 1. FIG. 17 is a circuit diagram of an embodiment corresponding to FIG. 16, FIG. 18 is an explanatory diagram of FIG. 1, and FIG.
The figure is an explanatory diagram of FIG. 15. 1...Color amplifier, 2...1H delay line, 4...
...Adder, 5...Subtractor, 6...B-Y demodulator,
7...G-Y demodulator, 8...R-Y demodulator, 9...
...Voltage controlled oscillator, 11... Phase shifter, 12...
Burst gate, 13... Phase comparator, 14...
Low pass filter, 15...Sweeper circuit, 17
...Color killer signal generation circuit, 20...PAL
Switch, 21...Flip-flop, 22...
Switch, 23... Extraction drive means, P ₁ ...
Burst gate pulse, P ₃ ...Trigger pulse,
VR...Adjustment volume, 41...Volume connection line.

Claims (1)

[Claims] 1. For supplying a PAL carrier color signal or color subcarrier signal with the phase reversed every 1H to a color demodulator.
a PAL switch; a PLL color synchronization circuit that compares the phase of the output of a voltage-controlled oscillator for color subcarrier generation with the color burst and applies the output voltage as a control signal to the oscillator; and a color demodulator for the color demodulator. a detection means for detecting the synchronous/asynchronous state of the color synchronization circuit by a burst period output; and a detection means for forcibly reversing the switching operation of the PAL switch when activated by the asynchronous detection output of the detection means. By the reversing drive means and the detection output of the detection means at the time of non-synchronization.
a color amplifier that stops amplification operation for a PAL carrier color signal, a gain adjustment volume is connected to the color amplifier, and the detection output of the detection means is transmitted to the inversion drive through a line connected to the volume. A color signal circuit of a PAL color television receiver adapted to be applied to the means.