JPH0351288B2 - - Google Patents
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- Publication number
- JPH0351288B2 JPH0351288B2 JP60074375A JP7437585A JPH0351288B2 JP H0351288 B2 JPH0351288 B2 JP H0351288B2 JP 60074375 A JP60074375 A JP 60074375A JP 7437585 A JP7437585 A JP 7437585A JP H0351288 B2 JPH0351288 B2 JP H0351288B2
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- Prior art keywords
- electron beam
- semiconductor
- single crystal
- film
- crystal layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2907—Materials being Group IIIA-VA materials
- H10P14/2909—Phosphides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H10P14/382—Scanning of a beam
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2907—Materials being Group IIIA-VA materials
- H10P14/2911—Arsenides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3238—Materials thereof being insulating materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3418—Phosphides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3421—Arsenides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3451—Structure
- H10P14/3452—Microstructure
- H10P14/3458—Monocrystalline
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3466—Crystal orientation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H10P14/3818—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/90—Thermal treatments, e.g. annealing or sintering
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、絶縁体上に半導体単結晶層を形成す
る技術に係わり、特に疑似線状電子ビームを用い
た半導体単結晶層の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a technique for forming a semiconductor single crystal layer on an insulator, and particularly to a method for manufacturing a semiconductor single crystal layer using a pseudo-linear electron beam.
〔発明の技術的背景とその問題点〕
近年、半導体工業の分野においては、電子ビー
ムアニール技術を用いたSOI（Silicon On
Insulator）膜の形成技術の研究開発が盛んとな
つている。この技術では、シリコン単結晶基板上
にシリコン酸化膜やシリコン窒化膜等の絶縁膜を
形成し、その上に多結晶シリコン膜や非晶質シリ
コン膜等を堆積し、電子ビーム或いはレーザビー
ム等のビーム照射により、上記シリコン膜を溶融
再結晶化させてシリコン単結晶層を成長させる方
法を採つている。[Technical background of the invention and its problems] In recent years, in the field of semiconductor industry, SOI (Silicon On
Research and development into technology for forming insulator films is gaining momentum. In this technology, an insulating film such as a silicon oxide film or a silicon nitride film is formed on a silicon single crystal substrate, a polycrystalline silicon film or an amorphous silicon film is deposited on top of the insulating film, and then an insulating film such as an electron beam or a laser beam is deposited on top of the insulating film. A method is adopted in which the silicon film is melted and recrystallized by beam irradiation to grow a silicon single crystal layer.
ところで、従来の電子ビームアニール方法で
は、細く絞つた電子ビーム（ガウス分布）をＸ、
Ｙ方向に走査させて試料面内を均一にアニールし
ている。この場合、通常使用される電子ビームの
直径は10〜500［μｍ］程度であり、１回のビーム
走査で溶融できるシリコン膜の幅は大略上記ビー
ム径程度となるため、大面積単結晶層を得る目的
には不適当であつた。それは、走査線の重合わせ
の部分での結晶粒界の発生を抑止することが困難
なためである。 By the way, in the conventional electron beam annealing method, a narrowly focused electron beam (Gaussian distribution) is
The specimen surface is uniformly annealed by scanning in the Y direction. In this case, the diameter of the commonly used electron beam is about 10 to 500 [μm], and the width of the silicon film that can be melted in one beam scan is approximately the above beam diameter. It was inappropriate for the purpose of obtaining it. This is because it is difficult to suppress the occurrence of grain boundaries in areas where scanning lines overlap.
そこで最近、第１１図に示す如く細く絞つた電
子ビームをその走査方向と直交する方向に高速偏
向することにより、電子ビームを疑似的に線状化
し、幅広い溶融領域を形成する技術が有望視され
ている。この場合、線状化ビームの長さは高速偏
向の振幅により決定され、原理的にはその長さに
は制限はない。しかし、一定ビーム電流のスポツ
トビームを高速偏向させた場合、振幅の増大に伴
い、第１２図に示すように電子ビーム照射された
試料表面の温度は低下する。半導体結晶層を製造
するためには、半導体膜を十分に溶融する必要が
ある。従つて、高速偏向振幅を増大させるには、
ビーム電流を増大させなければならない。このよ
うな事情から、実際には、ビーム電流の限界（即
ち電子銃の輝度特性）により、線状化ビームの長
さは決定される。 Recently, as shown in Figure 11, a promising technology has been developed to create a pseudo-linear electron beam by deflecting a narrowly focused electron beam at high speed in a direction perpendicular to its scanning direction, thereby forming a wide molten region. ing. In this case, the length of the linearized beam is determined by the amplitude of the high-speed deflection, and in principle there is no limit to its length. However, when a spot beam with a constant beam current is deflected at high speed, as the amplitude increases, the temperature of the sample surface irradiated with the electron beam decreases as shown in FIG. In order to manufacture a semiconductor crystal layer, it is necessary to sufficiently melt the semiconductor film. Therefore, to increase the fast deflection amplitude,
Beam current must be increased. Under these circumstances, the length of the linearized beam is actually determined by the limit of the beam current (ie, the brightness characteristics of the electron gun).
一方、上記の疑似線状電子ビームによる単結晶
層の製造においては、ビーム照射された試料表面
の線状化ビームの長さ方向の温度分布の制御の問
題がある。元来、線状電子ビームエミツタを用
い、試料表面上に線状ビームを投影する線状電子
ビームを用いる方法に比べ、上記の疑似線状電子
ビームを用いる方法では、電子ビームの強度分布
の制御性は格段に優れているが、高速偏向に用い
る電圧波形によつて、電子ビームの強度分布は変
化する。第１３図は正弦波により高速偏向させた
場合の線状化方向のシリコン表面温度分布を示す
図である。正弦波の特性として振幅の両端付近に
２つの温度ピークが存在し、中央部はこれらの部
分よりも温度は低くなる。そのため、試料に電子
ビーム照射した際に疑似線状ビームの両端付近を
適切に溶融させた場合、中央付近は溶融されな
い。従つて、試料表面を均一にアニールすること
が困難である。 On the other hand, in the production of a single crystal layer using the above-mentioned pseudo-linear electron beam, there is a problem of controlling the temperature distribution in the length direction of the linearized beam on the surface of the sample irradiated with the beam. Originally, compared to the method using a linear electron beam that uses a linear electron beam emitter to project a linear beam onto the sample surface, the method using the pseudo-linear electron beam described above provides better control over the intensity distribution of the electron beam. However, the intensity distribution of the electron beam changes depending on the voltage waveform used for high-speed deflection. FIG. 13 is a diagram showing the silicon surface temperature distribution in the linearization direction when high-speed deflection is performed using a sine wave. As a characteristic of a sine wave, there are two temperature peaks near both ends of the amplitude, and the temperature in the center is lower than in these parts. Therefore, if the vicinity of both ends of the quasi-linear beam is appropriately melted when the sample is irradiated with an electron beam, the vicinity of the center will not be melted. Therefore, it is difficult to uniformly anneal the sample surface.
これを解決するためには、正弦波によらず、三
角波等の電子ビームの存在確率が振幅内の位置に
よらず一定な波形を用いる方法も考えられるが、
高速偏向周波数が高くなると、波形歪みが増大
し、正弦波の特性に近くなるため、上記の問題の
解決は困難である。高速偏向信号には、ＭHzオー
ダの周波数が必要である。それは、第１４図に示
すように瞬間的な電子ビームの存在位置（偏向波
形の位相）の違いにより試料表面温度の変動が大
きくなるためである。そして、この変動は〜２
［ＭHz］以上の周波数で無視し得る程小さくなる。 In order to solve this problem, it is possible to use a waveform such as a triangular wave, in which the existence probability of the electron beam is constant regardless of the position within the amplitude, instead of using a sine wave.
As the high-speed deflection frequency increases, waveform distortion increases and becomes closer to the characteristics of a sine wave, making it difficult to solve the above problem. High speed deflection signals require frequencies on the order of MHz. This is because, as shown in FIG. 14, the sample surface temperature fluctuates greatly due to the instantaneous difference in the position of the electron beam (the phase of the deflection waveform). And this variation is ~2
It becomes negligibly small at frequencies above [MHz].
このように、従来の疑似線状ビーム技術には上
記のような問題があり、均一性の良い半導体単結
晶層を得ることは困難であつた。 As described above, the conventional quasi-linear beam technique has the above-mentioned problems, and it has been difficult to obtain a semiconductor single crystal layer with good uniformity.
〔発明の目的〕
本発明の目的は、疑似線状ビームの長さ方向の
温度分布を制御して平坦なものにすると共に、電
子ビーム照射部の外周部での温度分布をなだらか
なものとすることができ、試料内に発生する熱歪
みを最小化し、良質な単結晶層を製造することの
できる半導体単結晶層の製造方法を提供すること
にある。[Object of the Invention] An object of the present invention is to control the temperature distribution in the length direction of the pseudo-linear beam to make it flat, and to make the temperature distribution at the outer periphery of the electron beam irradiation part gentle. An object of the present invention is to provide a method for manufacturing a semiconductor single crystal layer, which can minimize thermal strain generated within a sample and manufacture a high quality single crystal layer.
本発明の骨子は、電子ビームを一方向に高速偏
向させて疑似線状ビームを形成する際に、高速偏
向させる高周波電圧波形をそれよりも低い周波数
の波形で振幅変調（AM）させ、変調信号の制御
により線状化ビームの強度分布を制御し、これに
より均一で大面積の半導体単結晶層を形成するこ
とにある。
The gist of the present invention is to amplitude modulate (AM) the high-frequency voltage waveform used for high-speed deflection with a waveform of a lower frequency when deflecting an electron beam in one direction at high speed to form a pseudo-linear beam. The purpose of this method is to control the intensity distribution of the linearized beam, thereby forming a uniform, large-area semiconductor single crystal layer.
ビームの線状化方向のビーム強度分布を変化さ
せるには、第１図に示す如き変調信号の振幅Ｂと
基本波の振幅Ａとの大きさを制御することにより
実行することができる。第１図の波形は、
Ｙ＝（Ａ・sinω1t＋Ｂ）・sinω2t
で表わされる。ω1とω2とはそれぞれ変調波及び
基本波の周波数である。Ａ／Ｂは変調度ｍを表わ
す。第２図は変調度ｍをパラメータとしたときの
電子ビームの存在確率密度分布を示す。ここで
は、Ｂ＝１としている。ｍ＝０の振幅変調しない
場合、ビーム位置Ｙ＝１の位置に存在確率密度の
巨大なピークが存在し、中央部に近付く程なだら
かな分布となつている。このような強度分布の電
子ビームを照射したときの試料表面の温度分布が
前記第１３図に示すものとなる。なお、第１３図
で温度のピークが小さくなつているのは、被アニ
ール試料上で熱の拡散が生じるためである。 The beam intensity distribution in the beam linearization direction can be changed by controlling the amplitude B of the modulation signal and the amplitude A of the fundamental wave as shown in FIG. The waveform in FIG. 1 is expressed as Y=(A・sinω 1 t+B)・sinω 2 t. ω 1 and ω 2 are the frequencies of the modulated wave and the fundamental wave, respectively. A/B represents the modulation degree m. FIG. 2 shows the electron beam existence probability density distribution when the modulation degree m is used as a parameter. Here, B=1. When m=0 and no amplitude modulation is performed, there is a huge peak of the existence probability density at the beam position Y=1, and the distribution becomes gentler as it approaches the center. The temperature distribution on the sample surface when irradiated with an electron beam having such an intensity distribution is shown in FIG. Note that the reason why the temperature peak becomes smaller in FIG. 13 is that heat diffusion occurs on the sample to be annealed.
また、第２図からｍ＝0.2、ｍ＝0.5とｍを大き
くするに従い、上記の電子ビーム存在確率密度の
ピークは小さくなり、中央部での値との差は小さ
くなる。ピークが小さくなり中央部の値との差が
小さくなると、上記した熱拡散も加わり、被アニ
ール試料表面の温度分布はより均一なものとな
る。さらに、ピークが小さくなると、アニール領
域周辺との温度勾配も小さくなることになる。従
つて、第１３図に示すような温度分布の不均一性
はｍの値を最適化することにより大幅に減少し、
均一な半導体層の溶融ができるようになる。ｍの
値は大略0.2〜0.8程度の間が適切な条件を与える
が、その最適値はアニール試料の構造、温度条件
等により変化する。 Moreover, as m is increased from FIG. 2 to m=0.2 and m=0.5, the peak of the electron beam existence probability density becomes smaller, and the difference from the value at the center becomes smaller. When the peak becomes smaller and the difference from the value at the center becomes smaller, the above-described thermal diffusion is also added, and the temperature distribution on the surface of the sample to be annealed becomes more uniform. Furthermore, as the peak becomes smaller, the temperature gradient with respect to the periphery of the annealing region also becomes smaller. Therefore, the non-uniformity of temperature distribution as shown in Fig. 13 can be significantly reduced by optimizing the value of m.
It becomes possible to uniformly melt the semiconductor layer. Appropriate conditions are provided for the value of m between about 0.2 and 0.8, but the optimum value varies depending on the structure of the annealed sample, temperature conditions, etc.
ところで、上記のような基準電位に対し正負の
方向の波形が対称な単なる正弦波を変調波として
用いる場合、前記第２図に示す如く電子ビーム存
在確率密度のピークが常に一点に立ち、且つその
ピーク値は比較的大きなものとなる。そして、こ
のピークが溶融層内の温度分布を厳密に均一化す
ることを妨げる要因となる。 By the way, when a simple sine wave whose waveform in the positive and negative directions is symmetrical with respect to the reference potential as described above is used as a modulating wave, the peak of the electron beam existence probability density always stands at one point as shown in the above-mentioned FIG. The peak value will be relatively large. This peak becomes a factor that prevents the temperature distribution within the molten layer from becoming strictly uniform.
そこで本発明では、第３図に示す如く振幅変調
を複数回施した電気信号により高速偏向させた電
子ビームを用いている。この場合、前記第２図に
示す電子ビーム存在確率密度のピークが複数点に
立ち、且つそのピーク値が小さくなる。これによ
り、溶融領域の温度制御をより厳密に行うことが
可能となるのである。 Therefore, in the present invention, as shown in FIG. 3, an electron beam is used which is deflected at high speed by an electric signal subjected to amplitude modulation a plurality of times. In this case, the electron beam existence probability density shown in FIG. 2 has peaks at multiple points, and the peak value becomes small. This makes it possible to more precisely control the temperature of the melting region.
本発明はこのような点に着目し、絶縁基体上に
形成された多結晶若しくは非晶質の半導体膜に電
子ビームを走査してアニールする半導体単結晶層
の製造方法において、振幅変調を複数回施した電
気信号により前記電子ビームを一方向に偏向する
と共に、これと交差する方向に該ビームを半導体
膜上で走査させるようにした方法である。 The present invention focuses on these points, and in a method for manufacturing a semiconductor single crystal layer in which a polycrystalline or amorphous semiconductor film formed on an insulating substrate is annealed by scanning an electron beam, amplitude modulation is performed multiple times. In this method, the electron beam is deflected in one direction by an applied electric signal, and the beam is scanned over the semiconductor film in a direction crossing this direction.
また本発明は、上記方法を実施するための電子
ビームアニール装置において、電子銃から放射さ
れた電子ビームを集束制御するレンズ系と、上記
ビームを被アニール試料上で走査する第１の偏向
器と、上記ビームを上記走査方向と交差する方向
に高速偏向する第２の偏向器と、この第２の偏向
器に振幅変調を複数回施した電気信号を印加する
高周波電源とを設けるようにしたものである。 The present invention also provides an electron beam annealing apparatus for carrying out the above method, which includes: a lens system that controls focusing of the electron beam emitted from the electron gun; and a first deflector that scans the beam on a sample to be annealed. , a second deflector that deflects the beam at high speed in a direction intersecting the scanning direction, and a high-frequency power source that applies an electrical signal subjected to amplitude modulation a plurality of times to the second deflector. It is.
本発明によれば疑似線状ビームの長さ方向の温
度分布を制御（平坦なものに）することができ、
幅広い均一な半導体層の溶融・最凝固を達成する
ことができる。さらに、電子ビーム存在確率密度
のピークを複数で且つ小さなものとすることがで
きるので、溶融領域の温度制御をより厳密に行う
ことが可能となる。このため、残留熱歪みの小さ
い良質な半導体単結晶層を大面積に亙つて製造す
ることができる。更にまた、非接触温度センサで
検出したアニール温度に従つて最適アニール条件
を作り出すように変調波形を変化させることによ
り、アニール領域端部での周囲への熱拡散に起因
する温度低下を防止し、線状化ビームの長さ方向
の温度分布を完全に平均化することができ、その
ために均一な結晶成長が図られる。
According to the present invention, the temperature distribution in the length direction of the pseudo-linear beam can be controlled (made flat),
It is possible to achieve uniform melting and solidification of a wide range of semiconductor layers. Furthermore, since the electron beam existence probability density can have multiple peaks and be small, it is possible to more precisely control the temperature of the melting region. Therefore, a high quality semiconductor single crystal layer with small residual thermal strain can be manufactured over a large area. Furthermore, by changing the modulation waveform to create optimal annealing conditions according to the annealing temperature detected by the non-contact temperature sensor, a temperature drop caused by heat diffusion to the surroundings at the edge of the annealing region is prevented. The temperature distribution in the length direction of the linearized beam can be completely averaged, thereby achieving uniform crystal growth.
以下、本発明の詳細を図示の実施例によつて説
明する。
Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第４図は本発明の実施例に使用した電子ビーム
アニール装置を示す概略構成図である。図中３１
は電子銃であり、この電子銃３１から放射された
電子ビームは集束レンズ３２及び対物レンズ３３
により集束されて試料３４上に照射されると共
に、走査コイル（第１の偏向器）３５により試料
３４上で走査される。走査コイル３５は、実際に
はビームをＸ方向（紙面左右方向）に偏向するＸ
方向偏向コイルと、ビームをＹ方向（紙面表裏方
向）に偏向するＹ方向偏向コイルとから構成され
ている。また、集束レンズ３２の主面にはアパー
チヤマスク３６が配置され、電子銃３１とレンズ
３２との間にはビームをON−OFFするためのブ
ランキング電極３７が配置されている。 FIG. 4 is a schematic configuration diagram showing an electron beam annealing apparatus used in an embodiment of the present invention. 31 in the diagram
is an electron gun, and the electron beam emitted from this electron gun 31 is passed through a focusing lens 32 and an objective lens 33.
The beam is focused and irradiated onto the sample 34, and the sample 34 is scanned by a scanning coil (first deflector) 35. The scanning coil 35 actually deflects the beam in the X direction (left and right direction in the paper).
It consists of a directional deflection coil and a Y-direction deflection coil that deflects the beam in the Y direction (the front and back directions of the paper). Further, an aperture mask 36 is arranged on the main surface of the focusing lens 32, and a blanking electrode 37 for turning the beam on and off is arranged between the electron gun 31 and the lens 32.
ここまでの構成は通常の電子ビームアニール装
置と同様であり、本実施例装置がこれと異なる点
は、前記レンズ３２と走査コイル３５との間にビ
ームを高速偏向するための偏向板（第２の偏向
器）３８を設けたことにある。即ち、偏向板３８
は前記第１１図に示す如くＹ方向に対向配置さ
れ、ビームをＹ方向に高速偏向するものとなつて
いる。また、偏向板３８には後述する如く駆動系
（高周波電源）４０により高周波電圧が印加され
るものとなつている。なお、上記説明では偏向板
３８を１組としたが、これに加えビームをＸ方向
に高速偏向する偏向器を設けるようにしても良
い。また、ワーキングデイスタンスが十分大きい
場合、偏向板３８の代りに偏向板３９を前記偏向
コイル３５の下方に設けることも可能である。 The configuration up to this point is the same as a normal electron beam annealing device, and the difference in this embodiment device is that there is a deflection plate (second The reason is that a deflector) 38 is provided. That is, the deflection plate 38
are arranged opposite to each other in the Y direction as shown in FIG. 11, and deflect the beam in the Y direction at high speed. Furthermore, a high frequency voltage is applied to the deflection plate 38 by a drive system (high frequency power source) 40 as described later. In the above description, one set of deflection plates 38 is used, but in addition to this, a deflector that deflects the beam at high speed in the X direction may be provided. Furthermore, if the working distance is sufficiently large, a deflection plate 39 may be provided below the deflection coil 35 instead of the deflection plate 38.
第５図は上記偏向板３８に高周波電圧を印加す
るための高周波電源４０の回路構成を示すブロツ
ク図である。この電源４０は、発振器４１，４
２，４３、変調器４４，４５及び増幅器４６等か
ら構成されている。第１の発振器４１は第１の変
調波を出力するもので、この出力信号は第１の基
本波を出力する第２の発振器４２の出力信号と共
に第１の変調器４４に供給される。第１の変調器
４４では、上記第１の変調波により上記第１の基
本波が振幅変調される。そして、この被変調波
（第２の変調波）は、第２の基本波を出力する第
３の発振器４３の出力信号と共に第２の変調器４
５に供給される。第２の変調器４５では、上記第
２の変調波により上記第２の基本波が振幅変調さ
れる。第２の変調器４５で変調された被変調波
は、増幅器４６を介して増幅される。そして、こ
の増幅器４６の出力電圧が高周波電源４０の出力
として前記第２の偏向板３８に印加されるものと
なつている。 FIG. 5 is a block diagram showing a circuit configuration of a high frequency power source 40 for applying a high frequency voltage to the deflection plate 38. This power supply 40 is connected to oscillators 41, 4
2, 43, modulators 44, 45, an amplifier 46, etc. The first oscillator 41 outputs a first modulated wave, and this output signal is supplied to the first modulator 44 together with the output signal of the second oscillator 42 that outputs the first fundamental wave. In the first modulator 44, the first fundamental wave is amplitude-modulated by the first modulated wave. This modulated wave (second modulated wave) is transmitted to the second modulator 4 together with the output signal of the third oscillator 43 that outputs the second fundamental wave.
5. In the second modulator 45, the second fundamental wave is amplitude-modulated by the second modulated wave. The modulated wave modulated by the second modulator 45 is amplified via the amplifier 46. The output voltage of this amplifier 46 is applied to the second deflection plate 38 as the output of the high frequency power source 40.
ここで、第１の発振器４１の出力信号である第
１の変調波を第６図ａに示す如き波形とし、第２
の発振器４２の出力信号である第１の基本波の波
形を同図ｂに示す如く第１の変調波より周波数の
高いものとすると、第１の変調器４４で得られる
被変調信号の波形は同図ｃに示す如きものとな
る。そして、この被変調信号を変調波として用
い、第２の変調器４５により周波数の十分高い第
２の基本波を変調することによつて、前記第３図
に示す如き電気信号が得られるものとなつてい
る。 Here, the first modulated wave, which is the output signal of the first oscillator 41, has a waveform as shown in FIG.
If the waveform of the first fundamental wave, which is the output signal of the oscillator 42, has a higher frequency than the first modulated wave as shown in FIG. The result will be as shown in figure c. Then, by using this modulated signal as a modulating wave and modulating a second fundamental wave with a sufficiently high frequency using the second modulator 45, an electrical signal as shown in FIG. 3 can be obtained. It's summery.
次に、上記装置を用いたシリコン単結晶層の製
造方法について説明する。 Next, a method for manufacturing a silicon single crystal layer using the above apparatus will be described.
まず、前記偏向板３８に印加する信号として
は、50［ＭHz］の正弦波を第６図ｃ示す如き信号
で振幅変調させた波形を用いた。即ち、第１の発
振器４１の発振周波数を５［ＫHz］、振幅を５
［Ｖ］、第２の発振器４２の発振周波数を26［Ｋ
Hz］、振幅を15［Ｖ］とした。また、第３の発振器
４３の発振周波数を50［ＭHz］、振幅を40［Ｖ］と
した。 First, as a signal to be applied to the deflection plate 38, a waveform obtained by amplitude modulating a 50 [MHz] sine wave with a signal as shown in FIG. 6c was used. That is, the oscillation frequency of the first oscillator 41 is 5 [KHz], and the amplitude is 5 [KHz].
[V], and set the oscillation frequency of the second oscillator 42 to 26[K
Hz], and the amplitude was 15 [V]. Further, the oscillation frequency of the third oscillator 43 was set to 50 [MHz], and the amplitude was set to 40 [V].
この高速偏向の条件下で、150［μｍ］径のスポ
ツト電子ビームを高速偏向して長さ４［mm］の線
状化電子ビームを形成し、この電子ビームを用
い、ビーム加速電圧12［KV］、ビーム電流12［ｍ
Ａ］、走査速度100［ｍ／sec］で電子ビームアニー
ルの実験を行つた。 Under this high-speed deflection condition, a spot electron beam with a diameter of 150 [μm] is deflected at high speed to form a linearized electron beam with a length of 4 [mm]. ], beam current 12 [m
A], electron beam annealing experiments were conducted at a scanning speed of 100 [m/sec].
実験試料としては、第７図に示す如く面方位
（100）、５インチ径の単結晶Si５１上に1.3［μｍ］
厚のSiO2膜（絶縁膜）５２を堆積し、その上部
に0.6［μｍ］厚の多結晶Si膜（半導体膜）５３を
堆積し、その上部にキヤツプ層としての0.5［μ
ｍ］厚のＷ膜５４及び0.5［μｍ］厚のSiN膜５５
の２層膜を付けたものを用いた。 The experimental sample was 1.3 [μm] on a 5-inch diameter single-crystal Si51 with a plane orientation (100) as shown in Figure 7.
A 0.6 [μm] thick polycrystalline Si film (semiconductor film) 53 is deposited on top of it, and a 0.5 [μm] thick polycrystalline Si film (semiconductor film) 53 is deposited on top of it as a cap layer.
m] thick W film 54 and 0.5 [μm] thick SiN film 55
A two-layer film was used.
アニール後の試料では、幅3.7［mm］のシリコン
再結晶層が得られ、その表面状態も極めて平坦性
の優れたものであつた。また、多結晶シリコン膜
５３の下部のSiO2膜５２の一部を開口させた構
造の試料では、上記SiO2膜５２の開口部で基板
シリコンと直接接した多結晶シリコン膜５３の再
結晶時に基板から垂直にエピタキシヤル成長し、
次いでSiO2膜５２上のシリコン層も横方向にエ
ピタキシヤル成長する結果、この幅3.7［mm］の溶
融帯に含まれた領域中では、大面積の（100）方
位の単結晶層が得られた。 In the sample after annealing, a silicon recrystallized layer with a width of 3.7 [mm] was obtained, and its surface condition was extremely flat. In addition, in a sample having a structure in which a portion of the SiO 2 film 52 below the polycrystalline silicon film 53 is opened, during recrystallization of the polycrystalline silicon film 53 that is in direct contact with the substrate silicon at the opening of the SiO 2 film 52, Epitaxially grown vertically from the substrate,
Next, the silicon layer on the SiO 2 film 52 also grows epitaxially in the lateral direction, and as a result, a large-area (100) oriented single crystal layer is obtained in the region included in this 3.7 [mm] wide molten zone. Ta.
なお、この実施例では第２の変調波の形成のた
めに２つの正弦波を用いたが、これらの一方或い
は両方を三角波、多角形波、鋸歯状波にしても、
同様の効果が得られるのが確認された。 In this example, two sine waves were used to form the second modulated wave, but one or both of them may be a triangular wave, a polygonal wave, or a sawtooth wave.
It was confirmed that similar effects could be obtained.
次に、上述のアナログ的な変調方式でなく、よ
り進んだ技術であるパルス変調方式を利用し方法
について説明する。その典型的な例として、パル
ス符号変調（PCM）方式を応用した場合につい
て述べる。高周波電源としては、前記第５図に示
す発振器４１，４２及び変調器４４の代りに、第
８図に示す如く半導体メモリ（PROM）９１及
びDA変換器９２を用いた。この装置において、
まず任意の波形を量子化し、その強度を２進数に
変換したデータを半導体メモリ９１に格納させ
た。次いで、このデータを読出し、DA変換器９
２に通してアナログ量とし、これを変調器４５に
入力させて、発振器４３からの基本波を振幅変調
させた。この結果、前記のアナログ変調方式では
困難であつた、任意の波形の被変調波による高速
偏向が可能となつた。従つて、電子ビーム存在確
率分布を完全に自由に制御することができ、線状
化ビームの長さ方向の温度分布を完全に平坦化す
ることができた。 Next, a method using a pulse modulation method, which is a more advanced technology, instead of the analog modulation method described above will be described. As a typical example, we will discuss the case where pulse code modulation (PCM) is applied. As a high frequency power source, a semiconductor memory (PROM) 91 and a DA converter 92 as shown in FIG. 8 were used instead of the oscillators 41, 42 and modulator 44 shown in FIG. 5. In this device,
First, an arbitrary waveform was quantized, and the intensity was converted into a binary number and the data was stored in the semiconductor memory 91. Next, this data is read and the DA converter 9
2 to obtain an analog quantity, which was input to the modulator 45 to amplitude-modulate the fundamental wave from the oscillator 43. As a result, it has become possible to perform high-speed deflection using a modulated wave of an arbitrary waveform, which was difficult with the analog modulation method described above. Therefore, it was possible to completely freely control the electron beam existence probability distribution, and it was possible to completely flatten the temperature distribution in the length direction of the linearized beam.
次に、本発明の実施例について説明する。 Next, examples of the present invention will be described.
この実施例は、変調波形を予めメモリに格納し
ておいて利用する上記第２の実施例に代つて、コ
ンピユータ（CPU）を用いて任意波形を作り出
し、その波形（２進数で出力）をDA変換器に入
力させた後、振幅変調する方法である。高周波電
源としては、前記第８図に示すPROM９１の代
りに、第９図に示す如くCPU９３を用いればよ
い。 This embodiment uses a computer (CPU) to generate an arbitrary waveform and outputs the waveform (output in binary) as a DA, instead of the second embodiment in which the modulation waveform is stored in memory in advance and used. This method involves amplitude modulating the signal after inputting it to a converter. As a high frequency power source, a CPU 93 as shown in FIG. 9 may be used instead of the PROM 91 shown in FIG. 8.
この場合、半導体結晶層の形成時（電子ビーム
アニールの最中）に、常時最適アニール条件を作
り出すように波形をオンラインで変化させながら
電子ビームアニールを行うことができる。例え
ば、第１０図に示す如く電子ビームアニール中の
試料表面温度を非接触温度センサ４９等により常
時モニタし、その出力の大小に応じて、CPU９
３で電子ビーム存在確率密度分布の最適解を計算
し、その結果に応じた変調波形を出力させるよう
にすればよい。 In this case, during the formation of the semiconductor crystal layer (during electron beam annealing), electron beam annealing can be performed while changing the waveform online so as to constantly create optimal annealing conditions. For example, as shown in FIG. 10, the sample surface temperature during electron beam annealing is constantly monitored by a non-contact temperature sensor 49, etc., and depending on the magnitude of the output, the CPU 9
3, the optimum solution of the electron beam existence probability density distribution may be calculated, and a modulation waveform corresponding to the result may be output.
この方式は、特にアニール領域の端部での周囲
への熱拡散による温度低下に対する補正や、線状
化ビームをラスタ走査させた時の走査の重なる部
分での過度な加熱の補正を実行できる点が、均一
な結晶成長を行う上で効果的である。 This method has the advantage of being able to compensate for temperature drops due to heat diffusion to the surroundings, especially at the edges of the annealing region, and to compensate for excessive heating in areas where the scans overlap when the linearized beam is raster scanned. However, it is effective in achieving uniform crystal growth.
なお、本発明は上述した各実施例に限定される
ものではない。例えば、前記基本波（第２の基本
波）の周波数は50［ＭHz］に限定されるものでは
なく、前記第１３図に示したような試料表面温度
の変動を小さくできるものであればよい。温度変
動を小さくするためには、50［ＫHz］以上の周波
数が望ましい。変調波（第１或いは第２の変調
波）の周波数についても５［ＫHz］或いは26［Ｋ
Hz］に何等限定されるものではなく、基本波（第
１或いは第２の基本波）の周波数より低い周波数
であればよい。 Note that the present invention is not limited to the embodiments described above. For example, the frequency of the fundamental wave (second fundamental wave) is not limited to 50 [MHz], but may be any frequency that can reduce the variation in sample surface temperature as shown in FIG. 13. In order to reduce temperature fluctuations, a frequency of 50 [KHz] or higher is desirable. The frequency of the modulated wave (first or second modulated wave) is also 5 [KHz] or 26 [KHz].
Hz], and any frequency lower than the frequency of the fundamental wave (first or second fundamental wave) may be used.
また、電子ビームの偏向は、静電偏向に限ら
ず、電磁偏向であつてもよいのは勿論のことであ
る。さらに、基板材料としては、Siの代りに
GaAs、Ge、InP等の他の半導体材料を用いても
よい。また、絶縁膜としてのSiO2膜の厚みは適
宜変更可能であり、さらにSiO2膜の代りにSi−
Ｎ膜、Al2O3膜等の他の絶縁膜を用いることも可
能である。また、絶縁膜上に形成する半導体膜と
しては、多結晶シリコンの代りに非晶質シリコン
を用いることができ、さらにGe、GaAs、InP等
の他の半導体材料を用いることも可能である。そ
の他、本発明の要旨を逸脱しない範囲で、種々変
形して実施することができる。 Furthermore, it goes without saying that the deflection of the electron beam is not limited to electrostatic deflection, but may also be electromagnetic deflection. Furthermore, as a substrate material, instead of Si,
Other semiconductor materials such as GaAs, Ge, InP, etc. may also be used. Furthermore, the thickness of the SiO 2 film as an insulating film can be changed as appropriate, and Si-
It is also possible to use other insulating films such as N film and Al 2 O 3 film. Further, as the semiconductor film formed on the insulating film, amorphous silicon can be used instead of polycrystalline silicon, and other semiconductor materials such as Ge, GaAs, and InP can also be used. In addition, various modifications can be made without departing from the gist of the present invention.
第１図乃至第３図はそれぞれ本発明の概要を説
明するためのもので第１図は電子ビームを高速で
偏向するための電気信号として正弦波により振幅
変調された高速偏向波形を示す信号波形図、第２
図は振幅変調した高速偏向波形により形成した疑
似線状電子ビームのビーム長さ方向の電子ビーム
存在確率密度分布を示す特性図、第３図は振幅変
調を複数回施した高速偏向信号を示す信号波形
図、第４図は電子ビームアニール装置を示す慨略
構成図、第５図はその駆動系の回路構成を示すブ
ロツク図、第６図は第１の基本波を第１の変調波
で振幅変調して第２の変調波を形成するための方
法を示す信号波形図、第７図は被アニール試料の
概略構造を示す断面図、第８図は駆動系の回路構
成を示すブロツク図、第９図及び第１０図はそれ
ぞれ本発明の実施例を説明するためのもので第９
図は駆動系の回路構成を示すブロツク図、第１０
図は試料表面をモニタする例を示す概略構成図、
第１１図乃至第１４図はそれぞれ従来方法の問題
点を説明するためのもので第１１図は疑似線状ビ
ーム形成原理を示す模式図、第１２図は疑似線状
ビームの長さと試料表面温度との関係を示す特性
図、第１３図はビーム高速偏向中中心からの距離
と試料表面温度との関係を示す特性図、第１４図
は基本波周波数をパラメータとした時のビーム高
速偏向中心からの距離と試料表面温度との関係を
示す特性図である。
３１……電子銃、３２……集束レンズ、３３…
…対物レンズ、３４……被アニール試料、３５…
…偏向コイル（第１の偏向器）、３６……アパー
チヤマスク、３７……ブランキング電極、３８，
３９……偏向板（第２の偏向器）、４０……駆動
系（高周波電源）、４１，４２，４３……発振器、
４４，４５……変調器、４６……増幅器、４９…
…温度センサ、５１……単結晶Si基板、５２……
SiO2膜（絶縁膜）、５３……多結晶Si膜（半導体
膜）、５４，５５……キヤツプ層、９１……
PROM、９２……DA変換器、９３……CPU。
Figures 1 to 3 are for explaining the outline of the present invention, and Figure 1 is a signal waveform showing a high-speed deflection waveform whose amplitude is modulated by a sine wave as an electric signal for deflecting an electron beam at high speed. Figure, 2nd
The figure is a characteristic diagram showing the electron beam existence probability density distribution in the beam length direction of a quasi-linear electron beam formed by an amplitude-modulated high-speed deflection waveform. Figure 3 is a signal showing a high-speed deflection signal subjected to amplitude modulation multiple times. Waveform diagram, Figure 4 is a schematic configuration diagram showing the electron beam annealing device, Figure 5 is a block diagram showing the circuit configuration of its drive system, and Figure 6 shows the amplitude of the first fundamental wave with the first modulated wave. A signal waveform diagram showing a method for modulating to form a second modulated wave, FIG. 7 is a cross-sectional view showing the schematic structure of the sample to be annealed, FIG. 8 is a block diagram showing the circuit configuration of the drive system, and FIG. Figures 9 and 10 are for explaining embodiments of the present invention, respectively.
The figure is a block diagram showing the circuit configuration of the drive system.
The figure is a schematic configuration diagram showing an example of monitoring the sample surface.
Figures 11 to 14 are for explaining the problems of the conventional method, respectively. Figure 11 is a schematic diagram showing the principle of forming a quasi-linear beam, and Figure 12 is a diagram showing the length of the quasi-linear beam and the sample surface temperature. Figure 13 is a characteristic diagram showing the relationship between the distance from the center of high-speed beam deflection and the sample surface temperature, and Figure 14 is a characteristic diagram showing the relationship between the distance from the center of high-speed beam deflection and the sample surface temperature. FIG. 3 is a characteristic diagram showing the relationship between the distance and the sample surface temperature. 31... Electron gun, 32... Focusing lens, 33...
...Objective lens, 34... Sample to be annealed, 35...
...Deflection coil (first deflector), 36...Aperture mask, 37...Blanking electrode, 38,
39... Deflection plate (second deflector), 40... Drive system (high frequency power supply), 41, 42, 43... Oscillator,
44, 45...Modulator, 46...Amplifier, 49...
...Temperature sensor, 51...Single crystal Si substrate, 52...
SiO 2 film (insulating film), 53... polycrystalline Si film (semiconductor film), 54, 55... cap layer, 91...
PROM, 92...DA converter, 93...CPU.
Claims (1)
は非晶質の半導体膜に電子ビームを走査してアニ
ールする半導体単結晶層の製造方法において、振
幅変調を複数回施した電気信号により前記電子ビ
ームを一方向に偏向すると共に、これと交差する
方向に該ビームを前記半導体膜上で走査させ、一
方前記半導体膜のアニール時の温度を非接触温度
センサで常時検出し、この検出温度に基づいて最
適アニール条件を作り出すように前記電気信号の
変調波形を変化させながら電子ビームアニールを
行うことを特徴とする半導体単結晶層の製造方
法。 ２ 前記基体は、単結晶半導体基板上に絶縁膜が
形成されたものであることを特徴とする特許請求
の範囲第１項記載の半導体単結晶層の製造方法。 ３ 前記絶縁膜は、その一部に開口が形成された
ものであることを特徴とする特許請求の範囲第２
項記載の半導体単結晶層の製造方法。[Claims] 1. A method for manufacturing a semiconductor single crystal layer in which a polycrystalline or amorphous semiconductor film formed on an insulating surface of a substrate is annealed by scanning an electron beam, in which amplitude modulation is applied multiple times. Deflecting the electron beam in one direction by an electric signal, and scanning the beam on the semiconductor film in a direction crossing this direction, while constantly detecting the temperature of the semiconductor film during annealing with a non-contact temperature sensor, A method for manufacturing a semiconductor single crystal layer, characterized in that electron beam annealing is performed while changing the modulation waveform of the electrical signal so as to create optimal annealing conditions based on the detected temperature. 2. The method for manufacturing a semiconductor single crystal layer according to claim 1, wherein the base body is a single crystal semiconductor substrate on which an insulating film is formed. 3. Claim 2, wherein the insulating film has an opening formed in a part thereof.
A method for manufacturing a semiconductor single crystal layer as described in 1.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60074375A JPS61234034A (en) | 1985-04-10 | 1985-04-10 | Manufacture of semiconductor single crystal layer and electron beam annealing apparatus |
| US06/762,374 US4662949A (en) | 1985-02-15 | 1985-08-05 | Method of forming a single crystal semiconductor layer from a non-single crystalline material by a shaped energy beam |
| US06/904,942 US4746803A (en) | 1985-02-15 | 1986-09-08 | Method of forming a single crystal semiconductor layer from a non-single-crystalline material and apparatus for forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60074375A JPS61234034A (en) | 1985-04-10 | 1985-04-10 | Manufacture of semiconductor single crystal layer and electron beam annealing apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61234034A JPS61234034A (en) | 1986-10-18 |
| JPH0351288B2 true JPH0351288B2 (en) | 1991-08-06 |
Family
ID=13545357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60074375A Granted JPS61234034A (en) | 1985-02-15 | 1985-04-10 | Manufacture of semiconductor single crystal layer and electron beam annealing apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61234034A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58135629A (en) * | 1982-02-08 | 1983-08-12 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1985
- 1985-04-10 JP JP60074375A patent/JPS61234034A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61234034A (en) | 1986-10-18 |
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