JPH0351334B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a through-current prevention circuit for an output inverter.

[Prior Art] For example, some electronic watches use a circuit configuration as shown in FIG. 4 in order to prevent through-currents in output inverters for driving motors, alarms, etc. In the same figure, P1 and N1 are the P channel and N channel that constitute the output inverter, respectively.
Channel MOS transistor (hereinafter referred to as P
They are called channel and N channel. ), C1,
C2 is a gate capacitance, and G1 and G2 are gate circuits forming an R-S flip-flop circuit. T1
-T6 is an inverter, and inverters T1 to T4 are for delay.

By configuring as above, terminal a
When the input pulse shown in FIG. 5a is supplied to terminals b and c, the input pulse is delayed by gate circuits G1 and G2 and inverters T1 to T4, as shown in FIG. 5b and c, respectively. occurs. Fifth
As can be seen from the figure, the output from terminal b is earlier by time t1 at rise and delayed by time t2 at fall than the output from terminal c. During this time, both the P channel P1 and the N channel N1 are turned off, so that through current can be prevented.

In addition to the above, there is a technique disclosed in Japanese Patent Application Laid-Open No. 100514/1983. This is as shown in Figure 6.
By connecting a resistor R in series between the input side P channel P2 and N channel N2, and making the time constants on the gate input sides of P channel P1 and N channel N1 of the output inverter different, P channels P1 and N
This is to prevent channels N1 from being turned on at the same time.

In other words, as shown in the waveforms of each part in Fig. 7, P
N than the rise time of the gate input of channel P1
By slowing down the rise time of the gate input of channel N1, both are turned off at the same time between times t1 and t2.

[Problems to be Solved by the Invention] In the former conventional example, the time during which both channels are turned off is created by the delay time of the inverter, so this off time is very short. Therefore, P channel P1 and N channel N
There were cases in which the above-mentioned off time was not sufficient due to differences in the gate capacitance of the transistors 1 and variations in wiring resistance. In order to obtain a sufficient off time, there was a problem in that the number of stages of delay inverters had to be increased.

In the latter conventional example, for example, when a solar battery with large fluctuations is used as a power source, if the power supply voltage becomes higher than the specified value, the P channel P
1 and N channel N1 may be turned on at the same time.

This point will be explained below.

When the power supply voltage is VDD, input terminal a is “1”
When the signal is inverted from "0" to "0", the waveforms at various parts in FIG. 6 become as shown by solid lines in FIG. 7. That is, when the gate voltage of the P channel P2 becomes lower than the threshold voltage VTP, the P channel P2 is turned on, and the potential of the terminal b increases as shown by the solid line b. On the other hand, since the potential of terminal C is via resistor R, terminal b
It rises at a gentler slope.

At time t1, when the potential at terminal b exceeds the threshold voltage VTP of P channel P1, P
Channel P1 is turned off and at time t2,
When the potential at terminal c exceeds the threshold voltage VTN of N-channel N1, N-channel N1 is turned on.

Therefore, between time t1 and t2, P channel P
1 and N channels N1 are both turned off, preventing both channels from being turned on at the same time.

Next, suppose that the power supply voltage fluctuates and rises to VDD'. Then, the threshold voltages of P channels P1 and P2 follow this and shift to VTP'. That is, since the threshold voltage of the P channel is set to a voltage with a constant potential difference from VDD as a reference, it will increase by the amount that VDD increases.

Now, as the power supply voltage rises to VDD', the potentials of terminals b and c change to broken lines b' and
It rises steeply like c′. Then time t
At 2', the N channel N1 is turned on, and at a subsequent time t1', the P channel P1 is turned off. Therefore, during time t2'-t1', both channels P1 and N1 are turned on at the same time, causing a through current to flow.

In the present invention, even if the power supply voltage rises above the specified level,
It is possible to reliably prevent through current with a small number of elements.

[Means for Solving the Problems] The present invention provides gates that commonly receive input signals.
A current control MOS transistor formed by connecting the gate and source is connected between the channel and the N channel,
The connection points between the P channel and the N channel and the current control MOS transistor are connected to the gates of the P channel and N channel of the output inverter, respectively, and the current control MOS transistor is connected until there is no potential difference between the connection points. The above problem is solved by passing a constant current through the

[Example] In FIG. 1, P2 and N2 are a P channel and an N channel whose gates are commonly supplied with an input signal, respectively, and N3 is a depletion type N that constitutes a current control MOS transistor connected between the gate and source. It is a channel. The output side of P channel P2 is connected to the gate of P channel P1, and the output side of N channel N2 is connected to the gate of N channel N1.

FIG. 2 shows an equivalent circuit of FIG. 1.

Next, the operation will be explained. When terminal a is inverted from "1" to "0" as shown in Figure 3a, P channel P2 is turned on and the gate capacitance C in Figure 2 is
1 is rapidly charged as shown in Figure 3b. on the other hand,
The gate capacitor C2 is slowly charged by the constant current from the N channel N3 as shown in FIG. 3c.
Now, if the threshold voltage of the P channel P1 is set to the voltage Vtp shown in Figure 3b, and the threshold voltage of the N channel N1 is set to the voltage Vtn shown in Figure 3c, then the P channel P1 and the N channel N1 will change over time. Both are turned off during t3.

Next, when terminal a is inverted from "0" to "1", N channel N2 is turned on. Therefore, the gate capacitance C2 is rapidly discharged as shown in FIG. 3c. On the other hand, the gate capacitor C1 is slowly charged with a constant current by the N channel N3 as shown in FIG. 3b. Therefore, during time t4, P channel P1
and N channel N1 are both turned off.

As described above, when the level of terminal a is inverted, there is always time for both P channel P1 and N channel N1 to turn off, and through current can be prevented.

By the way, if a solar battery or the like is used as a power source,
If more light than necessary is irradiated, the power supply voltage will increase. However, in the present invention,
Because it uses a MOS transistor for current control,
Even if the power supply voltage increases, the through current can be reliably prevented without being affected by it. For example, suppose that the power supply voltage increases and the voltage of the input signal increases as indicated by the broken line in FIG. 8a. Then,
The gate voltage of the P channel P1 has a steep rise as shown by the broken line in FIG. 8b, but the gate voltage of the N channel N1
The rise curve of the gate voltage is the same as in the normal case, as shown in FIG. 8b, because of constant current charging.
Therefore, the time when both the P channel P1 and the N channel N1 are turned off is t3'. Furthermore, when the input signal a is cut off, the charges in the gate capacitor C1 are discharged at a constant current, so that the discharge curve remains the same as in normal times, as shown in FIG. 8b. Further, the discharge curve of the gate capacitance C2 is also the same as in normal times, so the time during which both channels P1 and N1 are both off is t4'.

In this way, even if the power supply voltage increases, the channels P1 and N1 will not be turned on at the same time, and through current can be reliably prevented.

Note that a depletion type P channel may be used as the current control MOS transistor.

[Effects] According to the present invention, it is possible to prevent the through current of the output inverter with an extremely simple configuration.

Moreover, even if the power supply voltage used rises, it will not be affected by it and can reliably prevent through current.
This is particularly effective when solar cells are used as the power source.

Further, if the current control MOS transistor is provided near the gate of the transistor of the output inverter, the wiring for the gate input terminal can be routed for a long time, making the layout easier.

[Brief explanation of drawings]

Fig. 1 is an electric circuit diagram showing an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of Fig. 1, Fig. 3 is a voltage waveform diagram for explaining operation, and Fig. 4 is a conventional circuit configuration. FIG. 5 is a time chart for explaining the operation of FIG. 4. FIG. 6 is an electric circuit diagram showing an example of another conventional circuit configuration.
This figure is a voltage waveform diagram showing voltage waveforms of various parts in the circuit of FIG. 6, and FIG. 8 is a voltage waveform diagram showing voltage waveforms of various parts when the power supply voltage increases in the present invention. P1, P2...P channel MOS transistor,
N1, N2...N channel MOS transistor,
N3...MOS transistor for current control.

Claims (1)

[Claims] 1. A current control MOS in which a P-channel MOS transistor and an N-channel MOS transistor whose gates are commonly supplied with an input signal are connected in series, and the gate and source are connected.
A transistor is connected between the P-channel MOS transistor and the N-channel MOS transistor, and a first connection point between the P-channel MOS transistor and the current control MOS transistor is connected to the gate of the P-channel MOS transistor of the output inverter. A second connection point between the N-channel MOS transistor and the current control MOS transistor is connected to the gate of the N-channel MOS transistor of the output inverter, and the current control MOS transistor is connected to the first A through-current prevention circuit for an output inverter, characterized in that a constant current flows until the potential difference disappears, regardless of the value of the potential difference between the connection point and the second connection point.