JPH0351921A - Runaway preventing device for cpu system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] {Industrial Field of Application} The present invention relates to a runaway prevention device for a CPU system using a microprocessor or the like that employs a so-called vector interrupt method.

(Prior art) The main memory of a system using a microprocessor is
As shown in the figure, a ROM 201 and a RAM 202 are used, and the ROM 201 stores an initial program loader for initialization operations as well as interrupt vectors. Furthermore, within the RAM 202 there is an area 203 to which the interrupt vectors in the ROM 201 are transferred and stored.

During initialization operations such as power-on, the microprocessor transfers the interrupt vector in the ROM 201 to the area 203 by the initial program loader, and for subsequent interrupts, searches for the corresponding interrupt vector in the area 203 and handles this interrupt. It responds to interrupts by executing the program indicated by the vector.

On the other hand, a microprocessor system is usually provided with a watchdog timer as a runaway monitoring circuit, and when a runaway is detected, it interrupts the microprocessor and performs runaway processing based on an interrupt vector for runaway processing.

However, when a runaway occurs in the microprocessor system as described above, the microprocessor may run out of control and rewrite the interrupt vector in area 203 until the watchdog timer detects the runaway. Even if a runaway is detected after rewriting has occurred in this way and an attempt is made to interrupt the microprocessor to perform processing using the interrupt vector for runaway processing, the interrupt vector for runaway processing will change to other data. Because
Furthermore, a problem occurred in that the vehicle ran out of control and became uncontrollable.

(Problems to be Solved by the Invention) As mentioned above, in the conventional CPU system, the interrupt vector for runaway processing is located in the data rewritable area, and the CPU
In some cases, the interrupt vector is rewritten with different data from when U runs out of control to when the runaway is detected.

Therefore, when a runaway is detected and the interrupt vector area is read, other data is stored in this area, causing further runaway and causing the problem to become uncontrollable.

The present invention was made to solve the problems of conventional CPU systems, and its purpose is to provide a runaway prevention device for a CPU system that can accurately handle runaway when runaway occurs. It is.

[Structure of the Invention] (Means for Solving the Problems) A first memory having an area in which an interrupt vector is written, a runaway monitoring circuit that monitors runaway of the CPU, and an interrupt to the CPU from the runaway monitoring circuit. The corresponding CP
a second memory in which interrupt vectors including interrupt vectors for runaway processing related to processing to be performed by U are written in advance; and during an initialization operation, the interrupt vectors of the second memory are transferred to the area of the first memory. Detects whether the initialization operation performed by this CPU has been completed,
A write inhibit means for inhibiting writing by the CPU to at least an area in the area of the first memory in which the interrupt vector for runaway processing is stored after the end is detected, and the CPU system A runaway prevention device was installed.

(Function) According to the above configuration, the interrupt vector is transferred during the initialization operation, and it is possible to instruct subsequent processing for interrupts to be performed by the CPU, and after this transfer operation is completed, the interrupt vector for runaway processing is stored. The area in which the interrupt has occurred becomes write-inhibited, the interrupt vector is protected, and accurate runaway processing can be performed after the runaway is detected.

(Example) Hereinafter, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of the main parts of the CPU system. 1 indicates a CPU such as a microprocessor, and 8 indicates a memory. The memory 8 represents the RAM 202 in FIG. 2, and although the ROM 201 is not shown here, various buses. It is connected to the CPU by control signals. Further, since the contents of the data have already been explained, their explanation will be omitted.

The address data output from the address/data terminal AD of the CPUI is the address latch time Fl! I2 is latched and applied to address terminal A of memory 8 and address decoder 3 via address bus 10. Similarly,
Data output from address/data terminal AD is applied to input/output terminal I/O of memory 8 via address/data multiplex bus 9.

When address decoder 3 receives address data corresponding to an area other than area 203 shown in FIG. 2 in memory 8, it outputs an L level signal to signal line 10A, and when address data corresponding to area 203 is received, Signal line 1
Outputs an L level signal to 0B. Reference numeral 4 indicates a write inhibit signal generation circuit, which stops upon receiving the start signal of the initialization operation via the signal line 20. From this point on, the CPUI counts the time to complete the initialization operation, and after counting up, the signal line 13 The signal is caused to transition from H level to L level.

The signals on the signal lines 10B and 13 are logically summed by an OR gate 18 and applied to an AND gate 17 via a signal line 12. Signal lines 10A and 12 given to AND gate 17
The signals are logically ANDed and sent to the memory 8 via the signal line 11.
is applied to the chip select terminal C1.

Signal line 21 from CPUI status terminal 82 to SO
A status signal is output to the bus controller 5 via. Based on the status signal, the bus controller 5 outputs a word signal (L) via the signal line 14 and a write signal (L) via the signal line 15 in accordance with the read/write cycle of the CPUI. The read signal is signal line 2
2 as a disable signal for the write inhibit signal generating circuit 4, and is applied to the read terminal RD of the memory 8 via the signal line 14. Signal line 15 from bus controller 5
The signal outputted via the runaway monitoring circuit 7 is logically ANDed with the runaway detection signal provided from the runaway monitoring circuit 7 in the OR gate 6, and is provided to the write terminal WR of the memory 8 via the signal line 19. The runaway monitoring circuit 7 detects runaway of the CPUI using a watchdog timer or the like, and its output signal is applied to a non-maskable interrupt terminal NMI of the CPUI via a signal line 16.

In the CPU system configured in this way, when the power is turned on, the initial program loader explained in FIG.
Processing such as transferring the data to area 203 of (RAM 202) is performed. At this time, the write inhibit signal generating circuit 4 is in the counting operation of the timer and its output is at H level, so the address data of area 203 is given to the address decoder 3 and a signal at L level is given from the signal line 10B. Even if the output of the OR gate 18 is L level,
Since the output of the AND gate 17 also becomes L level, the memory 8 is chip-selected and can be written to.

When the initialization operation as described above is completed, the timer of the write inhibit signal generation circuit 4 times out and an H level signal is output to the signal line 13, and when the address data of the area 203 is given to the address decoder 3, the OR gate 1
8 and the output of AND gate 1γ are set to H level, and writing to memory 8 is prohibited. In addition, when successive data is written to the area 203 of the memory 8, the write inhibit signal generation circuit 4 is given a disable signal from the bus controller 5 via the signal line 22, and the signal on the signal line 13 is set to L level. The signal becomes L level and reading becomes possible.

Further, when the runaway monitoring circuit 7 detects a runaway of the CPUI, its output becomes H level and a H level signal is given to the write terminal WR of the memory 8 to inhibit writing, and the CPUI cannot be masked. An H level signal is given to the interrupt terminal NMI, and based on this, the CPU searches for an interrupt vector for runaway processing in the area 203, and based on this, performs various save operations and performs processes such as stopping the system. conduct.

Note that in this embodiment, writing to the entire area 203 is prohibited, but at least the storage area for interrupt vectors for runaway processing may be prohibited from writing.

Furthermore, the end of the initialization operation (more precisely, the end of interrupt vector transfer) may be detected not by the timer but by a notification from the CPUI or the like. Further, write prohibition control may be performed on the write terminal WR of the memory 8.

[Effects of the Invention] As explained above, according to the present invention, after the initialization operation,
Since the storage area for interrupt vectors for runaway processing is prohibited from writing, the vectors in the area will not be rewritten between runaway detection and runaway processing, and runaway processing after runaway detection can be performed accurately.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a CPU system to which an embodiment of the present invention is applied, and FIG. 2 is a diagram showing a memory map of the main memory of the CPU. l... CPU 2... Address latch circuit 3... Address decoder 4... Write inhibit signal generation circuit 5... Bus controller 7... Runaway monitoring circuit 8... Memory 201... ROM 202...RAM 203...Area

Claims (1)

[Scope of Claims] A first memory having an area in which an interrupt vector is written; a runaway monitoring circuit that monitors runaway of the CPU; a second memory in which interrupt vectors including interrupt vectors for runaway processing related to processing are written in advance; and during an initialization operation, transfer the interrupt vectors of the second memory to the area of the first memory; The CPU processes the interrupt that occurs thereafter using the interrupt vector of the area, and detects whether the initialization operation performed by this CPU is completed, and after detecting the completion, the CPU processes the interrupt vector of the area of the first memory. A runaway prevention device for a CPU system, comprising a write inhibiting means for inhibiting writing by the CPU to at least an area in which the interrupt vector for runaway processing is stored.