JPH0352216Y2 - - Google Patents

Description

[Detailed description of the invention] Industrial field of application The invention relates to an automobile control system in which automobile accessories such as lamps, indicators, and horns are shared and controlled by multiple control stations interconnected through transmission lines. In particular, the present invention relates to an automobile control system that prevents communication errors between control stations.

Prior Art The front of a car has headlights, horns, etc., the rear has tail lamps, stop lamps, etc., the instrument panel has various indicators, and the driver's seat has various operation switches, etc. be.

If such a large number of equipment were to be centrally controlled in one place, a large number of wires would have to be laid, which would be a heavy burden.

Therefore, as disclosed in Japanese Utility Model Application Publication No. 48-109629, for example, a control station is provided for each part of the automobile, and the control of the equipment of each part is shared between these control stations. It is proposed to install only the minimum number of wires necessary for control of the control station in the motor vehicle.

By the way, there are two types of control stations: a master station, which plays a central role, and a remote station, which plays a terminal role.The master station sends control data to each remote station, and the remote stations are equipped based on that control data. It is common to use a system configuration that outputs a drive signal to the product.

Problems with the conventional technology When the remote station outputs a drive signal to each equipment, each equipment operates accordingly.
They often generate relatively large noise during transient states of operation. For example, when the energization/cutoff state of a lamp or solenoid changes, or when a motor is started, relatively large noise is generated at these times.

This noise is particularly likely to get onto communication wires installed between control stations, so if it happens to be a time when communication is being performed, there is a problem in that it can cause communication errors.

Purpose of the invention The purpose of the invention is to provide a control system for an automobile that prevents communication errors from occurring due to noise during operation of equipment.

Composition of the Invention In the automobile control system of the invention, a large number of automobile equipment is divided into two or more groups, and the equipment belonging to each group is connected to each control station provided correspondingly to each group. In an automobile control system in which the control stations are connected by a transmission line so as to be able to cooperate with each other, each control station has a storage means for holding control data for operating equipment belonging to the control station; communication break detection means for detecting a break in communication with another control station; and a drive signal for outputting a drive signal based on control data held by the storage means to each equipment in a lump after detecting the break in communication. The configuration is characterized in that it includes an output means.

Operation When the control station is communicating with another control station, the control data is held in the storage means, but is not output as a drive signal to the equipment. Therefore, relatively large noise that occurs during a transient state in which the operating state of the equipment changes cannot be mixed into the transmission path during communication, and no communication errors occur.

When communication is interrupted, the system detects the break and outputs a drive signal all at once, so all the equipment operates at the same time. This generates relatively large noise, which mixes into the transmission path. However, since no communication is taking place at this time, no communication error occurs.

Embodiments Hereinafter, the present invention will be explained in more detail based on embodiments shown in the drawings. Here, FIG. 1 is a block diagram of the main parts of an automobile control system according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the format of line data, and FIG.
Figure 4 is a block diagram of the main parts of the remote station, Figure 4 is a circuit diagram of the main parts of the remote station, and Figure 5 is a circuit diagram of the main parts of the remote station.
The figure is a signal waveform diagram of each part of the circuit shown in FIG. 4. Note that the present invention is not limited to the embodiments shown in the figures.

As shown in FIG. 1, the control system 1 includes a master station (hereinafter referred to as MS) 2, remote stations (hereinafter referred to as RS) 3a, 3b,
3c and 3d are connected by a transmission line 4.

Power is supplied to the MS2, RS3a, 3b, . . . from a battery 5 via a power supply line 6.

The MS 2 is located, for example, in an engine room, and is connected to the engine operating state detection means 7. The engine state detection means 7 includes one that detects the presence or absence of an ignition pulse to detect whether the engine is running or stopped, or one that detects whether the ignition key is on or off.
Examples include a device that detects an off state to detect an engine running/stopping state, and a device that detects an output voltage of a generator to detect an engine running/stopping state.

RS3a, 3b... are respectively installed on the back side of the instrument panel, in the dash panel, in the engine room, and inside the trunk room, and are connected to nearby equipment in order to control them.

Communication between the MS2 and each RS3a, 3b, 3c, and 3d is performed by serial transmission.

The format of line data transmitted from MS2 to RS3a, 3b, . . . on transmission line 4 is as shown in FIG. 2, for example.

In other words, the first bit of the serial data is "L".
It is determined by the level and represents the starting bit. The 33rd bit is set to the "H" level and represents a stop bit.

The second and third bits are set to "L, H" or "H, L", the former representing the A block and the latter representing the B block. Each RS
3a, 3b, . . . are defined as either the A block or the B block.

The fourth bit represents the operating state of the engine; when it is "L", the engine is in a stopped state, and when it is "H", it shows that the engine is in an operating state.

The first to fourth bits are called a 0 address. Further, addresses 1 to 7 are assigned to every 4 bits after the 5th bit, and the total number of data blocks is 33 bits.

Normally, 33 bits are first sent as A block,
Subsequently, 33 bits are sent as B block, and one transmission is completed.

FIG. 3 is a block diagram showing the receiving part of the RS 3a, and the other RSs 3b, 3c, . . . have similar configurations.

RS3a is given a designation of A block or B block and an address of one of 1 to 7.

The decoder 13 detects whether it is an A block or a B block, and the decoder 22 detects whether it is its own address.

Serial data from MS2 is input to AND gate 11 via input buffer 10.

The output signal of the one-shot circuit 29 is input to the AND gate 11, and since this is normally "1", the serial data is passed through the AND gate 11 to the shift registers 12, 16 and the start edge detection circuit 29. is input.

The oscillator and frequency divider 24 generate a clock signal whose period matches the 1-bit width of the serial data. Initially, the output of the start edge detection circuit 20 is "1"; is input to the clear input of the frequency divider 24 and the address counter 21, so the frequency divider 24 and the address counter 21 output "0".

Therefore, no clock signal is input to shift registers 12 and 16.

When serial data is input to the input buffer 10, the start edge detection circuit 20 detects the edge of the first bit, sets the output to "0", and enables the frequency divider 24 and address counter 21.

At this time, the output of the address counter 21 is "0"
Therefore, the 0 address detection output of the decoder 22 is "1", and the clock signal is applied to the shift register 12 through the AND gate 25.

However, since the N address detection signal of the decoder 22 is "0", no clock signal is applied to the shift register 16.

Therefore, serial data is read into only the shift register 12 in order from the first bit.

When the first 4 bits corresponding to the 0 address are read into the shift register 12, the 0 address detection signal of the decoder 22 changes from "1" to "0", so the clock signal to the shift register 12 is stopped and the clock signal is read to the 0 address. The shift register 12 continues to hold the corresponding first four bits.

The decoder 13 detects an allocated block from the second and third bits of the 0 address held in the shift register 12, and if it matches the allocated block previously allocated to itself, it outputs an allocated block detection signal. Outputs "1".

When the allocation block detection signal becomes “1”,
In response to this and the fall of the 0 address detection signal, the latch 14 is triggered via the AND gate 26, and the 0 address held in the shift register 12 is
The fourth bit for voltage control is read out of the serial data corresponding to the address.

When “1” or “0” is read into the latch 14, the voltage control 15 will
The power supply voltage V _c of RS3a is switched to either a relatively high voltage or a relatively low voltage.

As explained with reference to FIG. 2, when the engine is running, the line data of "H" is input from MS2, thereby the latch 14 outputs "0", and when the output is "0", the voltage control 1
5 selects a relatively high voltage. Therefore, the noise margin is improved, and malfunctions are prevented regardless of noise caused by ignition pulses, plug sparks, etc. that accompany engine operation.

On the other hand, when the engine is in a stopped state, "L" is input as the line data, thereby the latch 14 outputs "1", and the voltage control 15
choose a relatively low voltage. Therefore, RS3a
power consumption is reduced.

Although the noise margin is also lowered by lowering the power supply voltage _Vc , malfunctions do not occur because noise such as ignition pulses associated with engine operation is not generated.

When the data read into the shift register 12 differs from its own allocation block, the latch 1
4 is not loaded, so it is not affected in any way.

Now, when the address is detected by the decoder 22 and assigned to itself, N
Outputs "1" as an address detection signal.

At this time, if the allocation block detection signal is also "1", the clock signal is applied to the shift register 16 through the AND gate 27, and the serial data is read.

When the assigned block is different from itself or has a different address, the AND gate 27 does not pass the clock signal, and the shift register 16 does not read the serial data.

Therefore, only the control data for itself is read into the shift register 16 and held. however,
Since latch 17 has not yet been loaded, the drive signal to the load will not change and the operating state of the equipment will not change.

When the address counter 21 counts the final bit of one block, it outputs a final bit signal.

When the final bit signal is output, the start edge detection circuit 20 is reset, stops the frequency divider 24 and address counter 21, and waits for the first bit of the next block.

In one transmission, several blocks are sent in succession, and when the last block is detected, the decoder 1
3 sets the final block detection signal to "1". For example, when A block and B block are successively transmitted at one time, when the decoder 13 detects the B block, the final block detection signal is set to "1".

When the final bit signal is output at the final bit of the final block, a trigger is applied to the latch 17 through the AND gate 28, and the control data held in the shift register 16 is latched.

The output of the latch 17 is applied to a load including a driver 19 via a buffer 18, and a drive signal to the load is output based on the control data sent thereby. Therefore, the equipment changes its operating state all at once.

In this way, after detecting the last bit of the last block in one transmission, all the equipment is put into a new operating state all at once, so even if a large transient noise occurs when the operating state changes, it will not cause a communication error. This will be prevented from happening.

The output signal of the AND gate 28 serves as a trigger for the latch 17 as described above, and also serves as a trigger for the one shot circuit 29.
outputs a signal that becomes "0" for a predetermined period of time (for example, 10 msec to 30 msec).

Therefore, the AND gate 11 is in a state in which it does not accept a line signal during the "0" output of the one-shot circuit 29 after the final bit of the final block of one transmission.

The reason for this is that for a certain period of time after the detection of the final bit of the final block, the loads are driven all at once, making it easy for transient noise to appear on the line.To avoid this, malfunctions can be avoided. This is because line data is not read during that period. Next, Figure 4 shows the third
This is a specific circuit example of RS3a shown in the figure.
It consists of a CMOS integrated circuit. Also,
FIG. 5 shows signal waveforms at various parts of the circuit example shown in FIG. 4.

First, immediately after the power is turned on, the power-on reset 41 defines an initial state.

In this initial state, the flip-flop 14 is at "1" and the voltage control signal (FIG. 5k)
becomes "1", the transistor 42 is turned off, and the voltage of the battery 5 is lowered by the Zener diode 43 to a relatively low voltage, which is applied to the power supply line 46 as the power supply voltage _Vc . Therefore, RS3a operates at a relatively low voltage and power consumption is reduced.

The flip-flop 20 outputs "1" until the first bit of serial data is input, and the frequency divider 24 and address counter 21 output "0".

When serial data is input, its 0 address portion is read into the shift register 12. If the second and third bit portions representing the block in the data at the 0 address are the own allocated block, the AND gate 13a outputs an allocated block detection signal. The own allocation block is determined by the setting of jumper 44.

When the fourth bit of line data is input to the shift register 12, the 0 address detection signal becomes "0", and the falling edge of the signal is detected by the AND gate 2.
6 is input. At this time, if the allocation block detection signal is "1", the fourth bit is read into the flip-flop 14.

For example, if the self-allocated block is A block and the 4th bit is ``H'' as line data, the 4th bit is ``0'' and is read into the flip-flop 14.
"0" is output as the voltage control signal.

Then, the transistor 42 turns on and the voltage of the battery 5 is supplied to the power supply line 46 with almost no voltage drop, so that the power supply voltage V _c
is a relatively high voltage.

MS2 sets the 4th bit of the 0 address to "H" as line data when the engine is in operation, so in the end, when the engine is in operation, RS
The power supply voltage V _c of 3a is a relatively high voltage. Therefore, the noise margin becomes large, and the device can operate without error regardless of noise caused by ignition pulses and the like.

As a result of switching the power supply voltage V _c from a relatively low voltage to a relatively high voltage, the output level after the 0 address becomes a high level, as shown in FIG. 5e or b.

Now, the address assigned to RS3a is set by the jumper 46.

When the block of serial data matches the self-assigned block and the count value of the address counter 21 is the self-address, a clock signal is applied to the shift register 16 through AND gates 27' and 27''. , serial data is read in. However, the serial data is only held in the shift register 16 and is not transmitted to the equipment.

When the last bit of one block, that is, the 33rd bit, is counted by the address counter 21, the 33rd bit detection signal becomes "1", which resets the flip-flop 20. The frequency generator 24 and address counter 21 are stopped.

When the next B block is input, its 0
The address is input to shift register 12.

Since block B is not its own allocated block, flip-flop 14 is not affected.
The shift register 16 is also not affected.

On the other hand, since block B is the final block,
When the final block detection signal becomes "1" and the address counter 21 detects the 33rd bit, the latch 17 is triggered via the AND gate 28.

Therefore, the data held in the shift register 16 is transferred to the latch 17 and outputted to the load side via the output buffer 18. Therefore, all the equipment changes to a new operating state all at once.

As shown after the 33rd bit of block B in FIG. 5, as a result of all the equipment changing their operating states all at once, a large amount of noise is added to the line data, and noise is also generated in the output of the input buffer 10.

However, since the transmission has already been completed, there is no error in the transmission, thereby preventing the occurrence of a communication error.

On the other hand, at the same time as the latch 17 is triggered, the one-shot circuit 29 is also triggered and a mask signal is output.

Therefore, the mask signal from the one-shot circuit 29 causes the noise-added signal to be cut off by the AND gate 11, so that the RS 3a is prevented from malfunctioning due to this.

Now, when the car engine is stopped, the MS
2 provides serial data to RS3a in which the fourth bit of the 0 address is set to "L" as line data.

Then, as shown in block A at the right end of FIG. 5, after the fourth bit is read into the shift register 12, the voltage control signal becomes "1" again.
Therefore, the transistor 42 is turned off, and the power supply voltage V _c is switched to a relatively low voltage.

Therefore, the power consumption of RS3a is reduced. Note that since the engine is in a stopped state, there is no noise such as ignition pulses, so even if the power supply voltage _Vc becomes low and the noise margin decreases, there will be no malfunction.

As can be understood from the above explanation, according to the vehicle control system 1, the equipment changes to a new operating state only after communication ends.
This prevents communication errors from occurring due to relatively large noises that occur during these changes.

Effects of the invention According to the invention, a large number of automobile equipment is divided into two or more groups, and the equipment belonging to each group is connected to each control station provided correspondingly to each group. In an automobile control system in which control stations are connected by transmission lines so as to be able to cooperate with each other, each control station has a storage means for holding control data to operate the equipment belonging to itself, and a storage means for holding control data for operating equipment belonging to the control station. communication break detection means for detecting a break in communication with the station; and drive signal output means for detecting the break in communication and outputting a drive signal based on control data held by the storage means to each equipment in a batch manner. A control system for an automobile is provided, which is characterized in that it is equipped with the following, thereby making it possible to prevent communication errors from occurring due to noise during operation of equipment.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the main parts of an automobile control system according to an embodiment of the present invention, Fig. 2 is an illustration of line data format, Fig. 3 is a block diagram of main parts of the remote station, and Fig. 4 is a block diagram of the main parts of the remote station. FIG. 5 is a signal waveform diagram of each part of the circuit shown in FIG. 4. Explanation of symbols, 1...Car control system, 2
... Master Station (MS), 3a, 3b,
3c, 3d,...Remote station (RS), 4...Transmission line, 13...Decoder, 13
b... Ant gate, 16... Shift register,
17...Latch, 18...Buffer, 19...Driver, 21...Address counter.

Claims (1)

[Claims for Utility Model Registration] A large number of automobile equipment is divided into two or more groups, and the equipment belonging to each group is connected to each control station provided correspondingly to each group, and each of the equipment is connected to each control station provided correspondingly to each group. In an automobile control system in which stations are connected by transmission lines so that they can cooperate with each other, each control station has a storage means for holding control data to operate its own equipment, and a storage means for storing control data for operating equipment belonging to the control station. a communication break detection means for detecting a break in communication with the storage means; and a drive signal output means for detecting the break in communication and outputting a drive signal based on control data held by the storage means to each equipment at once. An automobile control system comprising: