JPH0352238B2 - - Google Patents

Info

Publication number
JPH0352238B2
JPH0352238B2 JP21416483A JP21416483A JPH0352238B2 JP H0352238 B2 JPH0352238 B2 JP H0352238B2 JP 21416483 A JP21416483 A JP 21416483A JP 21416483 A JP21416483 A JP 21416483A JP H0352238 B2 JPH0352238 B2 JP H0352238B2
Authority
JP
Japan
Prior art keywords
copper plating
plating layer
layer
circuit pattern
sulfide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP21416483A
Other languages
Japanese (ja)
Other versions
JPS60107893A (en
Inventor
Takara Fujii
Takashi Kishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Chemical Products Co Ltd
Original Assignee
Toshiba Chemical Products Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Chemical Products Co Ltd filed Critical Toshiba Chemical Products Co Ltd
Priority to JP21416483A priority Critical patent/JPS60107893A/en
Publication of JPS60107893A publication Critical patent/JPS60107893A/en
Publication of JPH0352238B2 publication Critical patent/JPH0352238B2/ja
Granted legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 [発明の技術分野] 本発明は、セミアデイテイブ法による印刷配線
板の製造方法に係り、特に回路精度、スルーホー
ル信頼性の優れた印刷配線板の製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a printed wiring board by a semi-additive method, and particularly to a method for manufacturing a printed wiring board with excellent circuit accuracy and through-hole reliability.

[発明の技術的背景とその問題点] 従来、印刷配線板は、銅張積層板を素材とし、
回路パターンとなる部分にフオトレジスト、イン
クレジスト等を用いてレジストパターンを印刷
し、これを硬化させた後、塩化第二鉄や塩化第二
銅の水溶液を用いて印刷されていない露出部分を
エツチング除去して回路を形成するエツチドフオ
イル法が主流であつた。
[Technical background of the invention and its problems] Conventionally, printed wiring boards are made of copper-clad laminates,
A resist pattern is printed using photoresist, ink resist, etc. on the part that will become the circuit pattern, and after this is cured, the exposed parts that are not printed are etched using an aqueous solution of ferric chloride or cupric chloride. The etched oil method, in which circuits are formed by removing the metal, was the mainstream.

エツチドフオイル法では、素材となる銅箔の70
〜80%がエツチング除去されるため基板としての
コストが高くなることや、スルーホール部の接続
を電気銅メツキで行うため基板表裏の銅箔はメツ
キにより70〜80ミクロンの厚さとより、これがエ
ツチング処理で長時間を要することになり、アン
ダーカツトやオーバーハング等の現象をおこし、
回路精度の高い印刷配線板の製造には適さない等
まだ問題がある。
In the etched oil method, 70% of the copper foil used as the material is
~80% of the board is removed by etching, which increases the cost of the board, and since the through-holes are connected using electrolytic copper plating, the copper foil on the front and back of the board is 70 to 80 microns thick due to plating. Processing takes a long time, causing phenomena such as undercuts and overhangs.
There are still problems, such as not being suitable for manufacturing printed wiring boards with high circuit precision.

近年、上記エツチドフオイル法の欠点を解消
し、回路のフアインパターン化、低コスト化、省
資源化に対応すべく必要な回路のみを化学メツキ
及び電気メツキで形成するセミアデイテイブ法が
急速に発展してきた。セミアデイテイプ法は、ス
ルーホールを有する積層板上にアクリルニトリル
ゴムと、ノボラツク型フエノール樹脂、レゾール
型フエノール樹脂またはエポキシ樹脂などとの混
合物からなる熱硬化型ブタジエン系接着剤を塗布
し、加熱硬化せしめて接着剤層を形成し、この接
着剤層を親水化及び活性化処理し、更にスルーホ
ール内壁を含む全面に化学銅メツキ層を形成した
後、ホール内壁と所定の回路パターンとを除く全
面にメツキレジストを被覆する。次いで電気銅メ
ツキを施してホール内壁及び所定の回路パターン
に電気銅メツキ層を形成した後、前記レジストを
剥離し露出する化学銅メツキ層を過硫酸アンモニ
ウム等のエツチング液で溶解除去して印刷配線板
を製造する方法である。
In recent years, a semi-additive method has been rapidly developed in which only the necessary circuits are formed by chemical plating and electroplating in order to overcome the drawbacks of the etched oil method and respond to the fine patterning of circuits, cost reduction, and resource saving. . In the semi-day tape method, a thermosetting butadiene adhesive made of a mixture of acrylonitrile rubber and a novolac type phenolic resin, a resol type phenolic resin, or an epoxy resin is applied onto a laminate having through holes, and the adhesive is heated and cured. After forming an adhesive layer, making the adhesive layer hydrophilic and activating it, and further forming a chemical copper plating layer on the entire surface including the inner wall of the through hole, plating is applied to the entire surface except for the inner wall of the hole and the predetermined circuit pattern. Coat the resist. Next, electrolytic copper plating is applied to form an electrolytic copper plating layer on the inner wall of the hole and a predetermined circuit pattern, and then the resist is peeled off and the exposed chemical copper plating layer is dissolved and removed with an etching solution such as ammonium persulfate to form a printed wiring board. This is a method of manufacturing.

しかしながら、前記セミアデイテイブ法は、化
学銅メツキ層にこれと同じ材質の電気銅メツキ層
を形成させるため、化学銅メツキ層を過硫酸アン
モニウム等でエツチングする際、電気銅メツキ層
もエツチングされる欠点がある。しかも電気メツ
キされるスルーホール内壁は同様に電気メツキさ
れる回路パターンに比してエツチング液の液切れ
が悪いためエツチング度合いが回路パターンの2
〜5倍となる。特にスルーホールコーナー部はエ
ツチング液が溜りやすく、エツチング条件によつ
てはわずか1〜3ミクロンの化学銅メツキ層をエ
ツチングする間にコーナー部の電気銅メツキ層と
化学銅メツキ層の全てがエツチングされ、断線を
起こす場合もある。理論上フアインパターン化を
可能とするセミアデイテイブ法であるが実際の工
程ではまだまだ欠点が多い。
However, in the semi-additive method, an electrolytic copper plating layer made of the same material as the chemical copper plating layer is formed, so when the chemical copper plating layer is etched with ammonium persulfate, etc., the electrolytic copper plating layer is also etched. . Moreover, the inner wall of the through-hole that is electroplated has a lower degree of etching than the circuit pattern because the etching liquid drains more slowly than the circuit pattern that is similarly electroplated.
~5 times. In particular, the etching solution tends to accumulate in the corner areas of the through holes, and depending on the etching conditions, the electrolytic copper plating layer and the chemical copper plating layer in the corner areas may all be etched while etching a chemical copper plating layer of only 1 to 3 microns. , may cause wire breakage. Although it is a semi-additive method that theoretically enables fine patterning, there are still many drawbacks in the actual process.

[発明の目的] 本発明の目的は、上記セミアデイテイブ法の問
題点を解消し、回路パターン精度、スルーホール
信頼性に優れた印刷配線板の製造方法を提供しよ
うとするものである。
[Object of the Invention] An object of the present invention is to solve the problems of the above-mentioned semi-additive method and to provide a method for manufacturing a printed wiring board with excellent circuit pattern precision and through-hole reliability.

[発明の概要] 本発明は上記の目的を達成させるためには、電
気銅メツキ層表面にエツチング液に溶解しない又
は溶解しにくい保護層を形成させ、かつ、後工程
で保護層が容易に溶解剥離可能な工程を見い出せ
ばよいことに着眼し、鋭意研究を重ねた。その結
果、硫化アルカリ金属塩水溶液で処理することに
より、エツチング液には溶解しにくく、シアン化
アルカリ水溶液には容易に溶解除去できる硫化物
層を得ることができた。この硫化物層の形成によ
り、スルーホール内壁及び回路パターン上の電気
銅メツキ層のエツチングを防止して、回路パター
ン精度が良好でスルーホール信頼性の極めて高い
印刷配線板の製造方法を見い出した。
[Summary of the Invention] In order to achieve the above object, the present invention forms a protective layer that does not dissolve or is difficult to dissolve in an etching solution on the surface of the electrolytic copper plating layer, and that the protective layer is easily dissolved in a subsequent process. Focusing on finding a process that would allow for peeling, they conducted extensive research. As a result, by treatment with an aqueous alkali metal sulfide salt solution, it was possible to obtain a sulfide layer that was difficult to dissolve in an etching solution but could be easily dissolved and removed in an alkali cyanide aqueous solution. By forming this sulfide layer, etching of the electrolytic copper plating layer on the inner wall of the through hole and the circuit pattern is prevented, and a method for manufacturing a printed wiring board with good circuit pattern accuracy and extremely high through hole reliability has been discovered.

即ち、本発明は、スルーホールを有する接着剤
付積層板を親水化及び活性化処理し、スルーホー
ル内壁を含む全表面に化学銅メツキ層を形成した
後、スルーホール内壁と回路パターンを除く化学
銅メツキ層表面にメツキレジストのレジストパタ
ーンを被覆した後、更に前記スルーホール内壁と
回路パターン表面に電気銅メツキ層を形成してな
る基板全体を硫化アルカリ金属塩水溶液で処理し
て前記電気銅メツキ層表面に硫化物層を形成させ
た後、前記レジストパターンを剥離して露出した
前記化学銅メツキ層を過硫酸アンモニウム水溶液
で溶解除去し、次いでシアン化アルカリ水溶液処
理を施して前記硫化物層を溶解除去せしめること
を特徴とする印刷配線板の製造方法である。
That is, in the present invention, an adhesive-attached laminate having through holes is hydrophilized and activated, a chemical copper plating layer is formed on the entire surface including the inner walls of the through holes, and then a chemical copper plating layer is formed on the entire surface including the inner walls of the through holes and the circuit pattern. After coating the surface of the copper plating layer with a resist pattern of plating resist, further forming an electrolytic copper plating layer on the inner wall of the through hole and the surface of the circuit pattern, the entire board is treated with an aqueous solution of alkali metal sulfide to remove the electrolytic copper plating. After forming a sulfide layer on the layer surface, the resist pattern is peeled off and the exposed chemical copper plating layer is dissolved and removed with an aqueous ammonium persulfate solution, and then treated with an alkali cyanide aqueous solution to dissolve the sulfide layer. This is a method for producing a printed wiring board, which is characterized by removing the printed wiring board.

本発明をさらに詳しく説明する。 The present invention will be explained in more detail.

まず、メツキの下地として接着剤層を表面にも
つ積層板すなわち、接着剤付き積層板をつくる。
First, a laminate with an adhesive layer on its surface as a base for plating, that is, an adhesive-coated laminate is made.

紙フエノール基材、紙エポキシ基材、またはガ
ラスエポキシ基材の積層板に、接着剤として例え
ばアクリルニトリルゴムとノボラツク型、レゾー
ル型のフエノール樹脂又は/及びエポキシ樹脂と
からなり、必要に応じて微粉末シリカ、ジルコニ
ウム化合物を配合した樹脂を塗布、転写した接着
剤付きプリプレグを用いて同時成形等を行い接着
剤付き積層板を得る。この積層板にプレス等によ
つてスルーホールを設け、次いで接着剤層と化学
銅メツキ層の密着強度を上げるためにクロム酸−
硫酸、重クロム酸−硫酸、クロム酸−ホウフツ酸
等を用いて親水化処理を行い、次いで通常行われ
ている塩化第一スズ、塩化パラジウム、および塩
酸を含む活性化処理液を用いて活性化処理を行
う。
A laminate of paper phenol base material, paper epoxy base material, or glass epoxy base material is coated with an adhesive consisting of, for example, acrylonitrile rubber and a novolac type or resol type phenol resin or/and epoxy resin, if necessary. A resin containing powdered silica and a zirconium compound is coated and transferred, and the adhesive-attached prepreg is simultaneously molded to obtain an adhesive-attached laminate. Through-holes were formed in this laminate by pressing, etc., and then chromic acid was added to increase the adhesion strength between the adhesive layer and the chemical copper plating layer.
Hydrophilic treatment is performed using sulfuric acid, dichromic acid-sulfuric acid, chromic acid-boronic acid, etc., and then activated using a commonly used activation treatment solution containing stannous chloride, palladium chloride, and hydrochloric acid. Perform processing.

親水化及び活性化処理を施したスルーホールを
有する接着剤付き積層板全表面に化学銅メツキを
行い通常3〜5μm厚の化学銅メツキ層を形成さ
せる。次にスルーホール内壁と必要回路パターン
を除く化学銅メツキ層表面にメツキレジストのレ
ジストパターンを形成する。これはスルーホール
内壁と回路パターンの電気銅メツキを行うための
ものでスクリーン印刷等によつて行われる。
Chemical copper plating is applied to the entire surface of an adhesive-coated laminate having through-holes that has been subjected to hydrophilization and activation treatment to form a chemical copper plating layer with a thickness of usually 3 to 5 μm. Next, a resist pattern of plating resist is formed on the surface of the chemical copper plating layer except for the inner wall of the through hole and the necessary circuit pattern. This is for electrolytic copper plating of the inner wall of the through hole and the circuit pattern, and is performed by screen printing or the like.

次いでメツキレジストが被覆されていないスル
ーホール内壁と回路パターン部に電気銅メツキ層
を形成させる。電気銅メツキ浴としてはピロリン
酸銅浴、硫酸浴等が使用され、ピロリン酸銅浴は
メツキのつきまわりが良く緻密な電気銅が得ら
れ、またスルーホールの信頼性も良い。こうして
スルーホール内壁と回路パターン上に電気銅メツ
キ層を形成した基板全体を硫化アルカリ金属塩水
溶液で処理して電気銅メツキ上に硫化物層を形成
させる。本発明の第一のポイントはこの硫化処理
液として硫化アルカリ金属塩水溶液を使用するこ
とである。硫化アルカリ金属塩としては硫化カリ
ウム、硫化ナトリウム、硫化カルシウム、硫化リ
チウム、硫化マグネシウム、硫化バリウム等があ
り、これらを水溶液として用いる。また必要に応
じて塩化アンモニウム等緩衝作用を行う物質を添
加してもよい。その配合割合は、過硫酸カリウム
3〜20g/、塩化アンモニウム5〜100g/
で行うことが好ましい。処理方法としては浸漬が
一般的で通常常温で5分間程度浸漬すれば十分で
ある。次に前記メツキレジスト被膜を剥離して、
露出した化学銅メツキ層を過硫酸アンモニウム水
溶液で溶解除去する。本発明の第二のポイント
は、前記硫化アルカリ金属塩水溶液で形成せしめ
た硫化物層をシアン化アルカリの希釈水溶液で処
理溶解除去せしめることである。
Next, an electrolytic copper plating layer is formed on the inner wall of the through hole and the circuit pattern portion which are not covered with the plating resist. As the electrolytic copper plating bath, a copper pyrophosphate bath, a sulfuric acid bath, etc. are used, and the copper pyrophosphate bath provides good plating coverage and dense electrolytic copper, and also has good through-hole reliability. The entire substrate on which the electrolytic copper plating layer is formed on the inner walls of the through holes and the circuit pattern is treated with an aqueous solution of alkali metal sulfide to form a sulfide layer on the electrolytic copper plating. The first point of the present invention is to use an aqueous sulfurized alkali metal salt solution as the sulfiding solution. Examples of alkali metal sulfide salts include potassium sulfide, sodium sulfide, calcium sulfide, lithium sulfide, magnesium sulfide, barium sulfide, and the like, which are used as an aqueous solution. Further, a substance having a buffering effect such as ammonium chloride may be added as necessary. The mixing ratio is potassium persulfate 3-20g/ammonium chloride 5-100g/
It is preferable to do so. A common treatment method is immersion, and immersion for about 5 minutes at room temperature is usually sufficient. Next, peel off the plating resist film,
The exposed chemical copper plating layer is dissolved and removed with an aqueous ammonium persulfate solution. The second point of the present invention is that the sulfide layer formed with the aqueous alkali metal sulfide salt solution is removed by treatment with a dilute aqueous alkali cyanide solution.

シアン化アルカリとしては、シアン化カリウ
ム、シアン化ナトリウム等が用いられスプレー又
は浸漬で行われる。
As the alkali cyanide, potassium cyanide, sodium cyanide, etc. are used, and the treatment is carried out by spraying or dipping.

その他一般的な処理操作、例えば親水化処理後
の中和処理や活性化処理前の塩酸処理等を行うこ
とは、本発明の効果を損なうものではない。
Other general treatment operations, such as neutralization treatment after hydrophilic treatment and hydrochloric acid treatment before activation treatment, etc., do not impair the effects of the present invention.

以上のごとき工程を経て回路精度、スルーホー
ルの信頼性の優れた印刷配線板の製造方法を提供
することができる。
Through the above steps, it is possible to provide a method for manufacturing a printed wiring board with excellent circuit accuracy and through-hole reliability.

[発明の実施例] 以下、実施例により本発明をより具体的に説明
する。
[Examples of the Invention] Hereinafter, the present invention will be explained in more detail with reference to Examples.

実施例 紙エポキシ積層板(当社製EPL)にアクリル
ニトリルゴム40重量部、レゾール型フエノール樹
脂20重量部、ビスフエノール型エポキシ樹脂20重
量部、微粉末シリカ10重量部及び硬化剤10重量部
をメチルエチルケトン−トルエン混合溶剤で溶解
した化学メツキ用接着剤をデイツプ方式で塗布し
風乾後、160℃で40分間熱硬化して厚さ約30ミク
ロンの接着剤層を形成した。続いてこの接着剤層
付き積層板の所定個所にドリルでスルーホールを
あけた後、接着剤層をクロム酸−硫酸混液で親水
化処理し、常法に従つて活性化処理をした後、化
学銅メツキ液に浸漬し、2.0μの化学銅メツキ層を
スルーホール内壁を含む全面に形成した。その後
スルーホール内壁及び所定の回路パターンを除く
化学銅メツキ層全面にメツキレジストを被覆し
た。次いで5%硫酸水溶液で活性化し、電気銅メ
ツキ処理をしてスルーホール内壁及び回路パター
ンに電気銅メツキ層を形成した。次に硫化カリウ
ム15g/、塩化アンモニウム50g/を含む水
溶液に常温で5分間浸漬し電気銅メツキ層上に黒
色の硫化物層を得た。次に塩化メチレンを用いて
メツキレジストを剥離除去した後、20%過硫酸ア
ンモニウム液に浸漬して露出した化学銅メツキ層
を溶解除去した。
Example 40 parts by weight of acrylonitrile rubber, 20 parts by weight of resol type phenolic resin, 20 parts by weight of bisphenol type epoxy resin, 10 parts by weight of fine powder silica, and 10 parts by weight of curing agent were added to a paper epoxy laminate (EPL manufactured by our company) with methyl ethyl ketone. - A chemical plating adhesive dissolved in a toluene mixed solvent was applied using a dip method, air-dried, and then thermally cured at 160°C for 40 minutes to form an adhesive layer with a thickness of about 30 microns. Next, after drilling through-holes at predetermined locations in the adhesive layered laminate, the adhesive layer was treated to make it hydrophilic with a chromic acid-sulfuric acid mixture, activated in a conventional manner, and then chemically treated. A chemical copper plating layer of 2.0 μm was formed on the entire surface including the inner wall of the through hole by immersing it in a copper plating solution. Thereafter, a plating resist was applied to the entire surface of the chemical copper plating layer except for the inner walls of the through holes and a predetermined circuit pattern. Next, it was activated with a 5% aqueous sulfuric acid solution and subjected to electrolytic copper plating treatment to form an electrolytic copper plating layer on the inner wall of the through hole and the circuit pattern. Next, it was immersed in an aqueous solution containing 15 g of potassium sulfide and 50 g of ammonium chloride at room temperature for 5 minutes to obtain a black sulfide layer on the electrolytic copper plating layer. Next, the plating resist was peeled off using methylene chloride, and then the exposed chemical copper plating layer was dissolved and removed by immersion in a 20% ammonium persulfate solution.

この間電気銅メツキ層の硫化物層に変化は生じ
なかつた。次に10%シアン化カリウム水溶液に数
秒間浸漬処理し電気メツキ層表面の硫化物層を溶
解除去して印刷配線板を得た。
During this period, no change occurred in the sulfide layer of the electrolytic copper plating layer. Next, the sulfide layer on the surface of the electroplated layer was dissolved and removed by immersion treatment in a 10% potassium cyanide aqueous solution for several seconds to obtain a printed wiring board.

得られた印刷配線板におけるスルーホール内壁
及び回路パターンの電気銅メツキ層の厚さをエツ
チング処理前の電気銅メツキ層の状態と比較した
ところその厚さはほとんど変化しておらず、しか
もスルーホール内壁と回路パターンとの銅メツキ
厚さのバラつきは全く認められなかつた。第1図
及び第2図に示したごとく銅メツキ層が精度よく
付着していた。
The thickness of the electrolytic copper plating layer on the inner wall of the through hole and the circuit pattern in the obtained printed wiring board was compared with the state of the electrolytic copper plating layer before the etching process. No variation was observed in the copper plating thickness between the inner wall and the circuit pattern. As shown in FIGS. 1 and 2, the copper plating layer was deposited with high accuracy.

比較例 実施例と同様の方法で化学メツキ用接着剤付積
層板を作り、穴あけ、親水化、活性化、化学銅メ
ツキ、レジスト被覆、電気銅メツキ処理し、次に
硫化処理を施すことなくレジストを剥離後、過硫
酸アンモニウムで化学銅メツキ層を溶解除去し、
印刷配線板を得た。得られた銅メツキ層の精度は
第3図及び第4図に示したごとく芳しくなかつ
た。
Comparative Example A laminate with adhesive for chemical plating was made in the same manner as in the example, and subjected to drilling, hydrophilization, activation, chemical copper plating, resist coating, electrolytic copper plating, and then resist coating without sulfurization. After peeling off, the chemical copper plating layer is dissolved and removed using ammonium persulfate.
A printed wiring board was obtained. The precision of the copper plating layer obtained was not good as shown in FIGS. 3 and 4.

[発明の効果] 以上説明したごとく、本発明によれば非回路パ
ターン部である露出化学銅メツキ層部分のエツチ
ング時スルーホール内壁及び回路パターンの電気
銀メツキ層のエツチングを防止でき、回路パター
ンの精度が良好でスルーホール信頼性の極めて高
い印刷配線板を製造し得る方法を提供できるもの
である。
[Effects of the Invention] As explained above, according to the present invention, when etching the exposed chemical copper plating layer portion that is a non-circuit pattern portion, etching of the inner wall of the through hole and the electrolytic silver plating layer of the circuit pattern can be prevented, and the circuit pattern can be improved. It is possible to provide a method for manufacturing a printed wiring board with good precision and extremely high through-hole reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は本発明に係る印刷配線板の断
面図及び回路パターンの断面図をそれぞれ示し、
第3図、第4図は比較例の印刷配線板の断面図及
び回路パターンの断面図をそれぞれ示す。 1……基板、2……銅メツキ層。
1 and 2 respectively show a cross-sectional view of a printed wiring board and a cross-sectional view of a circuit pattern according to the present invention,
FIG. 3 and FIG. 4 respectively show a cross-sectional view of a printed wiring board and a circuit pattern of a comparative example. 1...Substrate, 2...Copper plating layer.

Claims (1)

【特許請求の範囲】[Claims] 1 スルーホールを有する接着剤付積層板を親水
化及び活性化処理し、スルーホール内壁を含む全
表面に化学銅メツキ層を形成した後、スルーホー
ル内壁と回路パターンを除く化学銅メツキ層表面
にメツキレジストのレジストパターンを被覆し、
更に前記スルーホール内壁と回路パターン表面に
電気銅メツキ層を形成してなる基板全体を硫化ア
ルカリ金属塩水溶液で処理して前記電気銅メツキ
層表面に硫化物層を形成させた後、前記レジスト
パターンを剥離して露出した前記化学銅メツキ層
を過硫酸アンモニウム水溶液で溶解除去し、次い
でシアン化アルカリ水溶液処理を施して前記硫化
物層を溶解除去せしめることを特徴とする印刷配
線板の製造方法。
1 After hydrophilizing and activating an adhesive-attached laminate with through holes and forming a chemical copper plating layer on the entire surface including the inner walls of the through holes, a layer of chemical copper plating is applied to the surface of the chemical copper plating layer excluding the inner walls of the through holes and the circuit pattern. Cover the resist pattern of the metal resist,
Further, the entire substrate formed by forming an electrolytic copper plating layer on the inner wall of the through hole and the surface of the circuit pattern is treated with an aqueous alkali metal sulfide salt solution to form a sulfide layer on the surface of the electrolytic copper plating layer, and then the resist pattern is A method for producing a printed wiring board, which comprises removing the exposed chemical copper plating layer by dissolving it in an aqueous ammonium persulfate solution, and then treating it with an alkali cyanide aqueous solution to dissolve and remove the sulfide layer.
JP21416483A 1983-11-16 1983-11-16 Method of producing printed circuit board Granted JPS60107893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21416483A JPS60107893A (en) 1983-11-16 1983-11-16 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21416483A JPS60107893A (en) 1983-11-16 1983-11-16 Method of producing printed circuit board

Publications (2)

Publication Number Publication Date
JPS60107893A JPS60107893A (en) 1985-06-13
JPH0352238B2 true JPH0352238B2 (en) 1991-08-09

Family

ID=16651290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21416483A Granted JPS60107893A (en) 1983-11-16 1983-11-16 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS60107893A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008185604A (en) * 2007-01-26 2008-08-14 Fujitsu Ltd Electronic apparatus

Also Published As

Publication number Publication date
JPS60107893A (en) 1985-06-13

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