JPH035260U - - Google Patents
Info
- Publication number
- JPH035260U JPH035260U JP6432589U JP6432589U JPH035260U JP H035260 U JPH035260 U JP H035260U JP 6432589 U JP6432589 U JP 6432589U JP 6432589 U JP6432589 U JP 6432589U JP H035260 U JPH035260 U JP H035260U
- Authority
- JP
- Japan
- Prior art keywords
- servo
- processing circuit
- signal
- signal processing
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
Landscapes
- Moving Of The Head To Find And Align With The Track (AREA)
- Optical Recording Or Reproduction (AREA)
Description
第１図は本考案の一実施例によるサーボ信号処
理回路を示すブロツク図、第２図は光デイスクの
記録フオーマツトを示す略線図、第３図は本考案
によるサーボ信号処理回路の動作を示す信号波形
図、第４図は従来のサーボ信号処理回路の動作の
説明に供する信号波形図である。
１……サーボ信号処理回路、４……光デイスク
、５……光ヘツド、６……サーボ信号再生回路、
７……ホールド回路、８……タイミング発生回路
、９……ローパスフイルタ。
FIG. 1 is a block diagram showing a servo signal processing circuit according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing the recording format of an optical disk, and FIG. 3 shows the operation of the servo signal processing circuit according to the present invention. Signal Waveform Diagram FIG. 4 is a signal waveform diagram for explaining the operation of a conventional servo signal processing circuit. 1... Servo signal processing circuit, 4... Optical disk, 5... Optical head, 6... Servo signal reproducing circuit,
7... Hold circuit, 8... Timing generation circuit, 9... Low pass filter.
Claims (1)
から、アナログ信号でなるエラー信号を形成する
サーボ信号処理回路において、 上記サーボエラー信号を上記所定期間内の、当
該所定期間に対して所定分短いホールド期間の間
ホールドして、上記エラー信号を形成するように
した ことを特徴とするサーボ信号処理回路。[Claims for Utility Model Registration] In a servo signal processing circuit that forms an error signal consisting of an analog signal from servo error signals that are discretely input at predetermined intervals, A servo signal processing circuit characterized in that the error signal is formed by holding the error signal for a predetermined short hold period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6432589U JPH035260U (en) | 1989-05-31 | 1989-05-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6432589U JPH035260U (en) | 1989-05-31 | 1989-05-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH035260U true JPH035260U (en) | 1991-01-18 |
Family
ID=31595169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6432589U Pending JPH035260U (en) | 1989-05-31 | 1989-05-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH035260U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63149415A (en) * | 1986-12-10 | 1988-06-22 | Canon Inc | rotating device |
-
1989
- 1989-05-31 JP JP6432589U patent/JPH035260U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63149415A (en) * | 1986-12-10 | 1988-06-22 | Canon Inc | rotating device |
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