JPH0353056U

JPH0353056U -

Info

Publication number: JPH0353056U
Application number: JP11407489U
Authority: JP
Priority date: 1989-09-28
Filing date: 1989-09-28
Publication date: 1991-05-22

Description

[Brief explanation of drawings]

第１図は本考案のデータ伝送装置の一実施例の
ブロツク図、第２図はＦＩＦＯバツフア中のデー
タ形式を示す図、第３図は第１図の実施例の動作
を示すタイミングチヤート、第４図は従来例のブ
ロツク図である。１……レシーバ、２……復調器、３……データ
、４……書込みクロツク、５……ＦＩＦＯバツフ
ア、６……データ、７……読出しクロツク、８…
…変調器、９……トランスミツタ、１０……フレ
ーム終了書込み手段、１１……セレクタ、１２…
…ワンシヨツト出力回路、１３……制御ゲート、
１４……フレーム終了ビツト、Ｄ０……フレーム
終了データ（ビツト）、Ｄ１……書込みデータ、
ＤＬＫ……書込みクロツク（あるいは終了データ
書込み用１クロツク）、Ｐ……フレーム終了通知
、ＥＮＡ……イネーブル信号。 FIG. 1 is a block diagram of an embodiment of the data transmission device of the present invention, FIG. 2 is a diagram showing the data format in the FIFO buffer, FIG. 3 is a timing chart showing the operation of the embodiment of FIG. 1, and FIG. FIG. 4 is a block diagram of a conventional example. 1... Receiver, 2... Demodulator, 3... Data, 4... Write clock, 5... FIFO buffer, 6... Data, 7... Read clock, 8...
...Modulator, 9...Transmitter, 10...Frame end writing means, 11...Selector, 12...
...One-shot output circuit, 13...Control gate,
14...Frame end bit, D0...Frame end data (bit), D1...Write data,
DLK...Write clock (or one clock for writing end data), P...Frame end notification, ENA...Enable signal.

Claims

[Claim for Utility Model Registration] The burst data output from the segment is received, regenerated by a demodulator, and written to a FIFO buffer. When a predetermined amount of data is accumulated in the FIFO buffer, the data is read from the FIFO buffer, and the data is read out by the modulator. In a data transmission device for relaying burst data that modulates and sends out data, when reception of one frame data is completed,
frame end writing means 10 for detecting this and writing a frame end bit into the FIFO buffer; 1. A data transmission device for relaying burst data, comprising frame interval insertion means 12 and 13.