JPH0353773A - Drive method for solid-state image pickup - Google Patents

Abstract

PURPOSE:To reduce the after image and to secure a black level signal stably by reading a signal charge of all photodetector sections simultaneously from a photodetector section to a vertical CCD register within the horizontal blanking period, collecting charges two adjacent photodetector sections into one and transferring the resulting charge in the vertical direction. CONSTITUTION:A potential well is formed to a location under 2nd and 3rd transfer electrodes to which clocks phiV2, phiV3 are applied for a period t0 in, e.g. a 1st field. Clocks phiV1, phiV3 are brought into an H level for a charge readout (TG) period for a period t3 to read the charge of an odd number and an even number photodiodes(PD) into the respective potential well. Then the clock phiV2 is brought into an M level for a period t4 to sum two charges thereby forming a potential well under the 2nd and 3rd transfer electrodes. The readout operation as above is implemented for the horizontal blanking(HBLK) period in both the 1st and 2nd fields. Thus, even when the readout is limited within the HBLK period, the TG period is extended and after image is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for driving a solid-state image sensor, and particularly to a method for driving an interline transfer type solid-state image sensor. [Prior art] An interline transfer type solid-state sensor with one quadrant is shown in Fig. 8(a).
As shown in , a two-dimensionally arranged photodiode (hereinafter referred to as PD) 81, a transfer gate 8 for reading out the signal charge accumulated in the PD to a vertical CCD register, and a Vertical COD register (hereinafter referred to as VC as appropriate) to be transferred to the horizontal CCD register
(referred to as VCCD) 83, and a horizontal CCD register 84 that transfers the signal charge received from the VCCD 83 to an output amplifier 86. FIG. 8(b) is a cross-sectional view taken along the x-y line of FIG. The vertical CCD register 83 is formed by the photodiode region 81a formed in the p-well 87, and by the vertical CCD region 83a provided in the p-well 87 and the vertical transfer electrode 82 which also serves as a transfer gate electrode. The gate 85 is formed by a transfer gate region 85a provided in the p-well and a vertical transfer electrode 82.

Note that two vertical transfer electrodes are assigned to each photodiode, and one of the electrodes is a voltage 1+ which also serves as a transfer gate electrode.

Next, a conventional driving method will be described with reference to FIGS. 9 to 1. FIG. 9(a) is a read timing chart for the first field, FIG. 10 is a potential diagram corresponding to each period in FIG. 9(a), and FIG. 9(b) is a read timing chart for the second field. The chart in Figure 11 is a physical diagram corresponding to each period in Figure 9(b)0). This vertical CCD register has a four-phase clock φ
It is driven by v1 to φV4, but the vertical transfer electrode is
A1 to A4, 81 to B4, . . . and vertical transfer electrodes An, Bn, Cn, Dn, . We will call them electrodes. Here, the first and third transfer electrodes also serve as transfer gates. First, for the first field, see Figure 9 (a> and
During the to period, which will be explained with reference to Figure 0, clocks φv1 and φV4 are at low level (hereinafter referred to as L level).
Since φV2 and φV3 are middle level (hereinafter referred to as M level), the 2 to which φV2 and φv3 are applied is
, a potential well is formed under the third transfer electrode. During the charge readout period of period t1 (hereinafter referred to as TG period), φV3 is set at a high level (hereinafter referred to as H level).
As, the accumulated charge Qs of the odd-numbered PD. QN+a
,... to VCCD, and then φV3 is set to M
Return to level and end the read operation. Next, in period t2, φV1 is set to M level, and φV1, φV2, φ
Potential wells are formed under the first to third transfer electrodes to which V3 is applied, and by setting φv3 to L level during the t3 period, potential wells are formed under the first and second transfer electrodes. Subsequently, in the t4 period, potential wells are formed under the 1st, 2nd, and 4th transfer electrodes by setting φV4 to M level, and in the t5 period, φ■2 is set to L level, and 1,
Create a potential well under the fourth transfer electrode. Here, 3
Charge Qs read out at the th transfer electrode. QN+2
, ... are reversely transferred to the bottom of the first and fourth transfer electrodes. By setting φV1 to H level in the TG period of the t6 period, the charges QN+! of even-numbered PDs are transferred from the transfer gate. , QNo, . ..., and then sets φv1 to M level to end the read operation. In period t7, by setting φV2 to M level, potential wells are formed under the 1st, 2nd, and 4th transfer electrodes. Then, during period t8, φV4 is set to L level to form potential wells under the first and second transfer electrodes. Furthermore, in the t9 period, φV3 is set to M level, and in the tlo period, φV1 is set to L level, and the added charges are transferred to 2, 3 through the potential wells under the 1 to 3rd transfer electrodes.
Transfer to the potential well under the th transfer electrode. After this, the combined signal charge is transferred to the horizontal CCD register toward the right side of the figure using the usual four-phase drive CCD driving method. Next, the second field will be explained. In the second field, as shown in FIG. 11, the combinations of PDs to which the accumulated charges are added are different. Therefore, in the second field, after the first charge readout, the charges are transferred in the forward direction, the second charge readout is performed, and then the charges are once transferred in the reverse direction. Thereafter, the combined charge is transferred to the right side using the same transfer method as in the first field, and together with the first field, the interlace is completed. Note that it is desirable to perform these read operations within the horizontal blanking period indicated by HBLK in FIG. Therefore, reading by the third transfer electrode is performed during the optical black signal period immediately before the blanking period.

[Problems to be Solved by the Invention] In the above-described conventional method for driving a solid-state image sensor, when reading accumulated charges from a photodiode to a vertical CCD resistor, the readout period is a blanking period and an optical black signal period immediately before the blanking period. Therefore, when reading out the accumulated charges of two photodiodes separately and adding them together during field accumulation readout, it is not possible to lengthen the TG period for reading out the accumulated charges from the photodiodes to the vertical CCD register, resulting in afterimages. growing. In the conventional driving method, the signal charge was also read out during the optical black signal period.
It was not possible to secure a stable black level. In addition, recently, a high-speed shutter using a vertical overflow drain (VOD) structure is sometimes used, and when this is used, the storage time of the two PDs is different, resulting in a line step difference. Furthermore, in the conventional driving method, between the first charge readout and the second charge readout, Td=t 1+t
Since there is a time difference given by 2+t3+t4+t5,
The drawback was that the vertical resolution decreased, making it difficult to obtain clear images, especially for subjects moving at high speed.
[Means for Solving the Problems] The present invention includes a plurality of light receiving sections arranged in a matrix in the horizontal and vertical directions, and a plurality of columns that receive signal charges from the light receiving sections and transfer the signals in the vertical direction. vertical CCD
A solid-state image pickup device comprising: a register; and a horizontal CCD register coupled to one end of the plurality of columns of vertical CCD registers and configured to receive signal charges line by line from the plurality of columns of vertical CCD registers and transfer the signal charges in the horizontal direction. In the driving method, the signal charges of all the light receiving parts are simultaneously read out from the light receiving part to the vertical CCD register within the horizontal blanking period, and the charges of each two adjacent light receiving parts are combined into one, and then the signal charges are read out in the vertical direction. It is to be transferred to. [Example] Next, an example of the present invention will be described with reference to the drawings. 1(a) and 1(b) are timing charts showing the driving method of the first embodiment of the present invention, FIG. 1(a) is the first field, and FIG. 1(b) is the second field. This shows the timing of each clock when reading. Moreover, FIGS. 2 and 3 are diagrams showing the potential under each transfer electrode at the timings of FIG. 1 (a) and FIG. 1 (b), respectively. The clocks φv1 and φ■4 are at L level, and φV2 and φV3 are at M level, and potential wells are formed under the second and third transfer electrodes to which φV2 and φV3 are applied. During the tl period, φV2 is set to L level, a potential well is formed under the third transfer electrode, and in the t2 period, φ■1 is set to M level, and the potential well is placed below the first and third transfer electrodes, that is, it also serves as a transfer gate electrode. It is formed under the transfer electrode, and then φV1 is formed in the TG period in the t3 period.
, by setting φv3 to H level, the charges of the odd-numbered and even-numbered PDs are read from the transfer gate to the respective potential wells, and by setting φV1 and φv3 to M level, the readout is completed. In period t4,
By setting φv2 to M level, the two charges are added together, φ■1 is set to L level in period t5, and 2,
Create a potential well under the third transfer electrode.

After this, the combined charge is transferred to the horizontal CCD register toward the right side of the figure using the normal four-phase drive CCD transfer method. Next, charge reading in the second field will be explained with reference to FIG. 1(b) and FIG. 3. tO~t3
The period up to the period is the same as in the first field. In period t4, φV4 is set to M level and the two charges are added together. In period t5, φv1 is set to L level and the potential well is set to the third and fourth transfer electrodes. Give form to the bottom. Subsequently, in period t6, φV2 is set to M level to form potential wells under the second to fourth transfer electrodes, and then, in period t7, φv4 is set to L level, thereby increasing the charge by two or three times.
The th! It is transferred to the potential well formed at the bottom. After this, this combined charge is also transferred to the right in the figure, and together with the first field, it is possible to complete the interlacing. As shown in FIG. 1, the above read operation is performed in the horizontal blanking period indicated by HBLK in FIG. 1 for both the first and second fields. Since all the PD accumulated charges are read out in the first read operation, even if the readout is limited to the horizontal blanking period, the TO period can be lengthened, and afterimages can be reduced. Furthermore, by reading out data simultaneously, the amount of accumulated charge in odd-numbered PDs and even-numbered PDs can be equalized, and line level differences can be prevented. In particular, VOD
When performing a high-speed electronic shutter operation using the structure, the above-mentioned structure of the present invention is extremely effective because any difference in PD storage time tends to be affected. FIGS. 4(a) and 4(b') are timing charts showing the driving method of the second embodiment of the present invention regarding the first field and the second field, respectively, and FIGS. are diagrams showing the potential under each transfer electrode at the times shown in FIGS. 4(a) and 4(b), respectively. The difference between this embodiment and the first embodiment is that during the t1 period, the potential well is placed under the third transfer electrode to which φV3 is applied. The difference is that it is formed as follows (this example).
In the first embodiment, a potential well is formed under the third transfer electrode, and after forming a potential well under the first transfer electrode, charges are successively read out to those potential wells. , a potential in the same direction is applied twice to the same first transfer electrode, which may cause the p-well to sway. On the other hand, in the second embodiment, after forming potential wells under the first to third transfer electrodes, φV2 is set to L level and 1
~A potential well is formed under the third transfer electrode, and the charge is read out there, so there is little fluctuation in the p-well. FIG. 7(a) and FIG. 7(b) respectively show the third embodiment of the present invention.
5 is a timing chart showing a driving method regarding the first field and the second field in the embodiment. The difference between this embodiment and other embodiments is that when the charges of the PD are read out from the first and third transfer electrodes that also serve as transfer gate electrodes, during the readout operation, φV2 to φV4 are
This is the point at which this is considered an M level. By arranging the electrodes horizontally in this manner, even if there is variation in the depth of the potential wells formed under the first and third electrodes, the influence thereof can be reduced. In the above embodiment, a buried channel CCD with an n-type charge transfer region is used as a shift register, but the present invention is not limited to this, and the present invention is not limited to this. It can be similarly applied to those using a surface channel type CCD. [Effects of the Invention] As explained above, the present invention reads the signal charges of all PDs to VCCD simultaneously during the horizontal blanking period, and transfers the charges of two adjacent PDs together. Therefore, according to the present invention, the TG period can be lengthened and afterimages can be reduced. In this case, even if the TGwI interval is lengthened, the read operation can be completely contained within the blanking period, so according to the present invention, a stable black level signal can be obtained. Further, according to the present invention, since there is no time difference due to reading of two adjacent PDs, vertical resolution is improved. Furthermore, even when a high-speed electronic shutter using VOD is used, the storage time of the two PDs can be made the same, so line steps can be prevented.

[Brief explanation of drawings]

FIG. 1, FIG. 4, and FIG.
Timing chart showing the driving method of the third embodiment, the second
3 are potential diagrams for explaining the first embodiment, FIGS. 5 and 6 are potential diagrams for explaining the second embodiment, and FIG. 8(a) is a potential diagram for explaining the second embodiment. A plan view of the element, FIG. 8 (b) is a sectional view taken along the X-Y line, and FIG.
Timing chart showing the conventional driving method, FIG.
FIG. 11 is a potential diagram for explaining a conventional example. 81...Photodiode, 81a...Photodiode region, 82...Vertical transfer electrode, 8
3...Vertical CCD register, 83a...Vertical C
CD area, 84...Horizontal CCD register, 85...
...Transfer gate, 85FL...Transfer gate region, 86...Output amplifier, 87...
・P well, 88...n type semiconductor substrate, 89...
・Channel stopper.

Claims (1)

[Claims] a plurality of light receiving sections arranged in a matrix in the horizontal and vertical directions; a plurality of columns of vertical CCD registers that receive signal charges from the light receiving sections and transfer them vertically; and one end of the vertical CCD registers. The vertical C
A method for driving a solid-state image sensing device comprising a horizontal CCD register that receives charges from a CD register and transfers them toward an output section, the method comprising simultaneously transferring charges from the light receiving section to the vertical CCD register within a horizontal blanking period. 1. A method for driving a solid-state image sensing device, characterized in that the charges of all light receiving sections are read out, and the charges of two adjacent light receiving sections are combined into one and transferred in a vertical direction.