JPH035657B2 - - Google Patents
Info
- Publication number
- JPH035657B2 JPH035657B2 JP56044020A JP4402081A JPH035657B2 JP H035657 B2 JPH035657 B2 JP H035657B2 JP 56044020 A JP56044020 A JP 56044020A JP 4402081 A JP4402081 A JP 4402081A JP H035657 B2 JPH035657 B2 JP H035657B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- aluminum
- electrode wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明はアルミニウムを主成分とする電極配線
層を設けた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device provided with an electrode wiring layer mainly composed of aluminum.
半導体装置、とりわけ集積回路に於いてはアル
ミニウム(Al)膜が電極配線層として用いられ、
シリコンウエーハからpoly−Si(又はAl)−Al−
AlなどAlを多層に積層し多層配線として適用す
るものがある。通常、樹脂モールドされた状態
で、或いはパツケージに納めて空気抜きして用い
られるが、樹脂封止材料はその中に多量のNa+や
Cl-イオンを含み、これがAl膜を腐食する。 In semiconductor devices, especially integrated circuits, aluminum (Al) films are used as electrode wiring layers.
Poly-Si (or Al)-Al- from silicon wafer
There is a method in which Al such as Al is laminated in multiple layers and applied as a multilayer wiring. It is usually used in a resin molded state or in a package with air removed, but resin sealing materials contain a large amount of Na + and
Contains Cl - ions, which corrode Al films.
本発明は上記事情に鑑みてなされたもので、最
上層のAlを主成分とする電極配線のみをTiある
にはVとの合金で覆い、これを防止するようにし
たものである。その際多層のAl膜の最上層のみ
を合金化するのは多層のAl膜全てを合金で覆う
と合金化によりAlが食われることによる配線の
高抵抗化が甚大になり、しかも下層のAl配線は
線巾が細く(最上層のAl配線は下地の凹凸によ
るパターン精度を考慮して、又、上層では配線が
まとめられているため巾広である)、合金化した
場合高抵抗化が著しいため最上層のみ合金化を施
すことが望ましいからであり。又、Na+やCl-イ
オンによる腐食も最上層のみ遷移金属との合金層
で被覆するだけで充分だからである。 The present invention has been made in view of the above circumstances, and is designed to prevent this by covering only the uppermost layer of electrode wiring mainly composed of Al with an alloy of Ti or V. At this time, alloying only the top layer of the multilayer Al film is because if the entire multilayer Al film is covered with alloy, the alloying will eat away the Al, resulting in a significant increase in the resistance of the wiring, and furthermore, the lower layer Al wiring The line width is narrow (the top layer Al wiring takes into consideration the pattern accuracy due to the unevenness of the underlying layer, and the wiring is gathered in the upper layer, so it is wide), and when alloyed, the resistance increases significantly. This is because it is desirable to alloy only the top layer. In addition, it is sufficient to cover only the top layer with an alloy layer with a transition metal to prevent corrosion caused by Na + and Cl - ions.
以下、本発明の実施例を図面にもとずいて詳細
に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第1図は集積回路の多層配線の一例を示してい
る。1はシリコン基板ウエハであり、すでに拡散
工程を経て素子例えばバイポーラトランジスタ
(ここではPMP)が形成されている。2は絶縁膜
で、シリコンの酸化物や窒化物でできていて、素
子と電気的導通をとる部分には開孔が設けられて
いる。3は蒸着膜をパターニングして形成された
アルミニウムを主成分とする電極配線である。4
はリンガラスやCVD−SiO2膜、ポリイミド等の
絶縁膜即ちパシペーシヨン膜である。5はアルミ
ニウムを主成分とする第2層目の電極配線で絶縁
膜4に設けられた穴を通して第1層目の電極配線
3と接続している。この上に更に絶縁膜、電極配
線と交互に積み重ねても良いが、ここでは第2層
目の電極配線5が最上層であるとする。最上層の
電極配線の表面に遷移金属の金属間化合物層を形
成させるには、まず第2図に示すようにウエハ全
面に遷移金属6を蒸着する。次に適当な温度で熱
処理をして、第3図に示すように金属間化合物層
7を形成する。最後に、第4図に示すようにエツ
チング液で未反応遷移金属のみを除去する。この
のち全体を樹脂モールドする。 FIG. 1 shows an example of multilayer wiring of an integrated circuit. Reference numeral 1 denotes a silicon substrate wafer, on which elements such as bipolar transistors (in this case PMP) have already been formed through a diffusion process. Reference numeral 2 denotes an insulating film, which is made of silicon oxide or nitride, and has openings in the parts that are electrically connected to the element. Reference numeral 3 denotes an electrode wiring mainly made of aluminum and formed by patterning a deposited film. 4
is an insulating film, ie, a passivation film, such as phosphor glass, CVD-SiO 2 film, or polyimide. Reference numeral 5 denotes a second layer of electrode wiring mainly made of aluminum, which is connected to the first layer of electrode wiring 3 through a hole provided in the insulating film 4. Although insulating films and electrode wiring may be alternately stacked on top of this, it is assumed here that the second layer of electrode wiring 5 is the top layer. In order to form a transition metal intermetallic compound layer on the surface of the uppermost layer of electrode wiring, a transition metal 6 is first vapor-deposited over the entire surface of the wafer as shown in FIG. Next, heat treatment is performed at an appropriate temperature to form an intermetallic compound layer 7 as shown in FIG. Finally, as shown in FIG. 4, only unreacted transition metals are removed using an etching solution. After this, the whole thing is molded in resin.
具体的な作成例は次のようにして行なわれた。
拡散工程の完了したウエハの表面に厚さ5000Åの
二酸化シリコン膜を熱酸化で形成し、必要に応じ
て穴をあけた後、アルミニウムを1μm蒸着し、
通常の食刻法で4μmの巾の配線パターンにした。
次に、CVD(Chemical Vapor Deposition)法で
リンガラス(PSG)を厚さ1μm形成した。第1
層目の配線と第2層目の配線のコンタクトをとる
部分にリンガラスに穴をあけた後、蒸着、食刻に
より第2層目のアルミニウムの配線(厚さ1μm
パターン巾10μm)を形成した。金属間化合物形
成の為の遷移金属としてはチタン或いはバナジウ
ムを用い、蒸着膜の厚さは1000Åであつた。金属
間化合物を形成させる熱処理は水素を10%含有す
る窒素雰囲気中で450℃、30分間行なつた。この
熱処理条件は、通常デバイスと配線とのオーミツ
クコンタクトを得るためのものと同じであり、両
者を兼ねて一度に行なうことができる。熱処理後
形成される金属間化合物層の厚さはチタンの場合
が約3000Åであつた。バナジウムを用いても良
い。未反応遷移金属(チタン或いはバナジウム)
の除去は弗酸(49%)と硝酸(70%)の体積比1
対20からなる溶液で行なつた。このときはアルミ
ニウムや酸化膜、リンガラスに対し、チタンやバ
ナジウムのエツチングレートが500倍以上なので、
未反応のチタンやバナジウムだけを除去すること
ができる。この溶液はチタンやバナジウムのエツ
チング時、激しく気泡を発生し、エツチング完了
と共に気泡が消滅するので、除去完了点がはつき
りとわかるという特徴がある。場合によつては最
上層の電極配線の上に更にリンガラスやポリイミ
ドのパツシベーシヨン膜を形成しても良い。 A specific example of preparation was performed as follows.
After completing the diffusion process, a silicon dioxide film with a thickness of 5000 Å is formed on the surface of the wafer by thermal oxidation, holes are made as necessary, and then aluminum is evaporated to a thickness of 1 μm.
A wiring pattern with a width of 4 μm was made using the usual etching method.
Next, phosphorus glass (PSG) was formed to a thickness of 1 μm using a CVD (Chemical Vapor Deposition) method. 1st
After making a hole in the phosphor glass at the contact point between the first layer wiring and the second layer wiring, the second layer aluminum wiring (1 μm thick) is formed by vapor deposition and etching.
A pattern width of 10 μm) was formed. Titanium or vanadium was used as the transition metal for forming the intermetallic compound, and the thickness of the deposited film was 1000 Å. The heat treatment to form the intermetallic compound was carried out at 450° C. for 30 minutes in a nitrogen atmosphere containing 10% hydrogen. The heat treatment conditions are generally the same as those for obtaining ohmic contact between the device and the wiring, and both can be performed at the same time. The thickness of the intermetallic compound layer formed after the heat treatment was approximately 3000 Å in the case of titanium. Vanadium may also be used. Unreacted transition metal (titanium or vanadium)
Removal of hydrofluoric acid (49%) and nitric acid (70%) at a volume ratio of 1
A solution consisting of 20 pairs was used. At this time, the etching rate of titanium and vanadium is more than 500 times that of aluminum, oxide film, and phosphorous glass.
Only unreacted titanium and vanadium can be removed. This solution generates a lot of bubbles when etching titanium or vanadium, and the bubbles disappear when etching is complete, so the point at which removal is complete can be clearly seen. In some cases, a passivation film of phosphor glass or polyimide may be further formed on the uppermost layer of electrode wiring.
このようにして得られたエポキシ樹脂(シリコ
ン系樹脂でも良い)で樹脂モールドされた配線を
信頼性寿命試験によつて従来のアルミニウムの配
線と比較した。温度85℃湿度85%の高温高湿槽中
で配線に電界がかかるような状態にして2000時間
までの断線不良発生率を調べたところ、チタンの
金属間化合物を有する配線では5%、バナジウム
の金属間化合物を有する配線では15%、従来のア
ルミニウム配線では85%となり、金属間化合物で
表面を被覆された配線が耐腐食性に優れているこ
とがわかつた。また別の信頼性試験でエレクトロ
マイグレーシヨンに対しても優れていることがわ
かつた。 The wiring resin-molded with the epoxy resin (silicon resin may also be used) thus obtained was compared with conventional aluminum wiring in a reliability life test. When we investigated the disconnection failure rate for up to 2,000 hours by subjecting the wiring to an electric field in a high-temperature, high-humidity tank at a temperature of 85°C and humidity of 85%, we found that wiring with titanium intermetallic compounds had a rate of 5%, while vanadium had a rate of 5%. The corrosion resistance of wiring with intermetallic compounds was 15%, and that of conventional aluminum wiring was 85%, indicating that wiring whose surfaces are coated with intermetallic compounds has excellent corrosion resistance. In addition, another reliability test revealed that it is also excellent against electromigration.
以上述べたように重要なことはアルミニウムよ
り高融点で緻密かつ耐腐食性のある配線の表面合
金属を形成することである。 As stated above, what is important is to form a surface alloy for wiring that has a higher melting point, is denser, and has better corrosion resistance than aluminum.
第1図〜第4図は金属間化合物で被覆した配線
を作製する工程を示すシリコンウエハの横断面図
である。
1……シリコン基板、、2……絶縁膜(酸化物
或いは窒化物)、3……アルミニウムを主成分と
する第1層目の電極配線、4……絶縁膜(リンガ
ラス或いはポリイミド)、5……アルミニウムを
主成分とする第2層目(最上層)の電極配線、6
……遷移金属、7……アルミニウムと遷移金属の
金属間化合物。
FIGS. 1 to 4 are cross-sectional views of a silicon wafer showing the process of producing wiring coated with an intermetallic compound. 1... Silicon substrate, 2... Insulating film (oxide or nitride), 3... First layer electrode wiring mainly composed of aluminum, 4... Insulating film (phosphorous glass or polyimide), 5 ...Second layer (top layer) electrode wiring mainly composed of aluminum, 6
...transition metal, 7...intermetallic compound of aluminum and transition metal.
Claims (1)
層配線として2層以上積層された半導体装置に於
いて、半導体装置最上層の前記アルミニウムを主
成分とする電極配線層のみをこの配線層とTiあ
るいはVとの合金層で被覆したことを特徴とする
半導体装置。1. In a semiconductor device in which two or more electrode wiring layers mainly composed of aluminum are laminated as multilayer wiring, only the electrode wiring layer mainly composed of aluminum, which is the uppermost layer of the semiconductor device, is mixed with this wiring layer and Ti or V. A semiconductor device characterized by being coated with an alloy layer of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4402081A JPS57159044A (en) | 1981-03-27 | 1981-03-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4402081A JPS57159044A (en) | 1981-03-27 | 1981-03-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57159044A JPS57159044A (en) | 1982-10-01 |
| JPH035657B2 true JPH035657B2 (en) | 1991-01-28 |
Family
ID=12679977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4402081A Granted JPS57159044A (en) | 1981-03-27 | 1981-03-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57159044A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1236962A2 (en) | 2001-03-01 | 2002-09-04 | National Agricultural Research Organisation (NARO) | Freeze-dried product and process and apparatus for producing it |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6390839A (en) * | 1986-10-03 | 1988-04-21 | Nec Corp | Manufacture of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54152984A (en) * | 1978-05-24 | 1979-12-01 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1981
- 1981-03-27 JP JP4402081A patent/JPS57159044A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1236962A2 (en) | 2001-03-01 | 2002-09-04 | National Agricultural Research Organisation (NARO) | Freeze-dried product and process and apparatus for producing it |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57159044A (en) | 1982-10-01 |
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