JPH035703B2 - - Google Patents
Info
- Publication number
- JPH035703B2 JPH035703B2 JP58122120A JP12212083A JPH035703B2 JP H035703 B2 JPH035703 B2 JP H035703B2 JP 58122120 A JP58122120 A JP 58122120A JP 12212083 A JP12212083 A JP 12212083A JP H035703 B2 JPH035703 B2 JP H035703B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- differential
- circuit
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
Landscapes
- Small-Scale Networks (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Bidirectional Digital Transmission (AREA)
Description
【発明の詳細な説明】
本発明は双方向信号線路に関し、特に信号線路
を複数路に拡張する回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bidirectional signal line, and more particularly to a circuit for expanding a signal line into multiple paths.
従来、この種の信号線路の拡張は、第１図に示
すように、送信／受信制御部の送信信号TxDに
ドライバ回路Ｄの入力を並列に接続し、受信信号
RxDにレシーバ回路Ｒの出力をワイヤードオア
接続する方式であつた。このような方式におい
て、システム構成により、必要とする双方向信号
線路L1′〜LN′の数が変化する場合の対応策とし
て、予め推定される最大数の信号線路を標準的に
装備しておくかまたは必要に応じて双方向信号路
を増すように装置を変更する等の処置が必要であ
つた。 Conventionally, this type of signal line expansion was done by connecting the input of the driver circuit D in parallel to the transmission signal TxD of the transmission/reception control section, as shown in Fig.
The method was to connect the output of the receiver circuit R to RxD using a wired-OR connection. In such a system, as a countermeasure when the number of required bidirectional signal lines L 1 ′ to L N ′ changes depending on the system configuration, the maximum number of signal lines estimated in advance is equipped as standard. Therefore, it was necessary to take measures such as changing the equipment to increase the number of bidirectional signal paths or increasing the number of bidirectional signal paths as necessary.
前者の方法においては、双方向信号線路が少な
くても済むシステムにおいては無駄が生じ、コス
ト高となる欠点があつた。また後者の方法におい
ては、柔軟に対応できる反面、生産の管理コスト
が増大する欠点があつた。特に後者の方法では、
既にユーザに出荷したシステムが双方向線路の拡
張を必要とした場合、装置を入れ替える等の処置
が必要となり、ユーザの費用負担が増大する等の
欠点があつた。 The former method has the drawback of being wasteful and increasing costs in systems that require fewer bidirectional signal lines. Although the latter method allows flexibility, it has the disadvantage of increasing production management costs. Especially in the latter method,
If a system that has already been shipped to a user requires expansion of the bidirectional line, measures such as replacing the equipment are required, which has the disadvantage of increasing the cost burden on the user.
従つて本発明の目的は、システム構築に柔軟に
対応でき、しかも生産コストを低減させる双方向
信号線路拡張回路を提供することにある。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a bidirectional signal line expansion circuit that can be flexibly adapted to system construction and that can reduce production costs.
本発明によれば、２系統の双方向信号線路のど
ちらか１つの双方向信号線路に線路拡張を制御す
るためのドライバ回路の出力を接続し、もう一方
の双方向信号線路に線路拡張を制御するためのレ
シーバ回路の入力及び線路拡張を制御するための
直流レベル検出回路の入力を接続し、前記レシー
バ回路の出力を、前記２系統の双方向信号線路と
同等の線路を複数個構築するための複数個のドラ
イバ回路の各々の入力に接続し、前記線路拡張を
制御するためのドライバ回路の入力に、前記２系
統の双方向信号線路と同等の線路を複数個構築す
るための複数個のレシーバ回路の各々の出力に接
続し、かつ、前記直流レベル検出回路の出力は、
直流レベル検出がなされているとき、前記２系統
の双方向信号線路と同等の線路を複数個構築する
ために設けられた、複数個のドライバ回路の出力
が電気的に線路に接続された状態になるように接
続し、かつ、直流レベル検出がなされていないと
きは、前記線路拡張を制御するためのドライバ回
路の出力が電気的に線路に接続されるようにする
ことを特徴とする双方向信号線路拡張回路が得ら
れる。 According to the present invention, the output of a driver circuit for controlling line expansion is connected to one of two bidirectional signal lines, and the line expansion is controlled to the other bidirectional signal line. In order to connect the input of a receiver circuit for controlling line expansion and the input of a DC level detection circuit for controlling line expansion, and to construct a plurality of lines equivalent to the two bidirectional signal lines for the output of the receiver circuit. a plurality of lines for constructing a plurality of lines equivalent to the two bidirectional signal lines, connected to the inputs of each of the plurality of driver circuits, and connected to the input of each of the plurality of driver circuits for controlling the line expansion. connected to each output of the receiver circuit, and the output of the DC level detection circuit is
When DC level detection is being performed, the outputs of multiple driver circuits provided to construct multiple lines equivalent to the two bidirectional signal lines described above are electrically connected to the lines. and when the DC level is not detected, the output of the driver circuit for controlling the line extension is electrically connected to the line. A line extension circuit is obtained.
次に本発明の一実施例を示す図面を参照して本
発明を詳細に説明する。 Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.
第２図を参照すると、鎖線Ｙの左側の部分は、
従来例と同様な２系統の双方向信号線路を有する
送信、受信制御部である。まず、この送受信制御
部の動作について、簡単に説明する。 Referring to FIG. 2, the part to the left of the dashed line Y is
This is a transmission/reception control section having two bidirectional signal lines similar to the conventional example. First, the operation of this transmission/reception control section will be briefly explained.
送信、受信制御部の送信信号出力TxDは、差
動出力型ドライバ１，１′の信号入力の各々に接
続され、送信可信号出力TxEは、差動出力型ド
ライバ１，１′のイネーブル信号入力の各々に接
続される。また、受信信号入力RxDは差動入力
型レシーバ２，２′の信号出力の各々に接続され
る。差動出力型ドライバの出力Ｘ，Ｚは、差動入
力型レシーバの入力に接続されるとともに終端抵
抗ｒに接続される。 The transmission signal output TxD of the transmission and reception control section is connected to each of the signal inputs of the differential output type drivers 1 and 1', and the transmission enable signal output TxE is connected to the enable signal input of the differential output type drivers 1 and 1'. connected to each of the Further, the received signal input RxD is connected to each of the signal outputs of the differential input type receivers 2 and 2'. Outputs X and Z of the differential output type driver are connected to the inputs of the differential input type receiver and to a terminating resistor r.
送信、受信制御部は、送信信号TxDを出力す
るために、送信可信号TxEを論理値「１」の状
態に保持し、差動出力型ドライバの出力が電気的
に接続された状態（以下「イネーブル状態」とよ
ぶ）にする。これにより、送信信号出力TxDの
論理値が、差動出力型ドライバ１，１′により、
出力Ｘ，Ｚ間に差電圧が生じるように変換して、
出力される。このとき、差動出力型ドライバの出
力Ｘ，Ｚ間の差電圧は、差動入力型レシーバ２，
２′により検出され、送信、受信制御部の受信信
号入力RxDに論理値で入力される。このとき外
部からの受信入力信号は、送信、受信制御部によ
り、不必要なものとして受けつけない。 In order to output the transmission signal TxD, the transmission/reception control section holds the transmission enable signal TxE at a logical value of "1" and maintains the state in which the output of the differential output driver is electrically connected (hereinafter referred to as " (referred to as "enabled state"). As a result, the logical value of the transmission signal output TxD is changed by the differential output type drivers 1 and 1'.
Convert so that a voltage difference occurs between outputs X and Z,
Output. At this time, the differential voltage between the outputs X and Z of the differential output type driver is the voltage difference between the outputs of the differential input type receiver 2,
2' and is input as a logical value to the reception signal input RxD of the transmission and reception control section. At this time, the reception input signal from the outside is not accepted as unnecessary by the transmission and reception control section.
次に鎖線Ｙの右部、すなわち双方向信号線路拡
張回路について説明する。この部分は、２系統の
双方向信号線路をL1〜LNのＮ個に拡張するため
に設けられたものである。従つて、双方向信号線
路L1〜LNの出力X′，Z′は、送受信制御部の出力
Ｘ，Ｚと同等の信号である。送受信制御部の出力
Ｘ，Ｚの１つは、差動入力型レシーバ３の入力
Ａ，Ｂ及び直流レベル検出回路４の入力と終端抵
抗ｒに接続される。また、送受信制御部の出力
Ｘ，Ｚの他の１つは、差動出力型ドライバ５の出
力と終端抵抗ｒに接続される。差動入力型レシー
バ３の出力Ｃは差動出力型ドライバD1〜DNの
各々の入力に接続され、直流レベル検出回路４の
出力Ｆは、差動出力型ドライバD1〜DNのイネー
ブル信号の各々の入力に接続されるとともに、イ
ンバータ回路６に接続される。差動出力型ドライ
バ５の入力Ｈは、差動入力型レシーバR1〜RNの
各々の出力に接続されている。また、インバータ
回路６の出力Ｇは差動出力型ドライバ５のイネー
ブル信号の入力に接続される。差動出力型ドライ
バD1〜DNの出力x1〜xN，z1〜zNは差動入力型レ
シーバR1〜RNの入力および終端抵抗ｒに各々接
続される。 Next, the right side of the chain line Y, that is, the bidirectional signal line extension circuit will be explained. This part is provided to expand the two-system bidirectional signal line to N lines L1 to LN . Therefore, the outputs X' and Z' of the bidirectional signal lines L 1 to L N are signals equivalent to the outputs X and Z of the transmission/reception control section. One of the outputs X and Z of the transmission/reception control section is connected to inputs A and B of the differential input receiver 3, an input of the DC level detection circuit 4, and a terminating resistor r. Further, the other one of the outputs X and Z of the transmission/reception control section is connected to the output of the differential output type driver 5 and the terminating resistor r. The output C of the differential input type receiver 3 is connected to each input of the differential output type drivers D 1 to D N , and the output F of the DC level detection circuit 4 is connected to the enable of the differential output type drivers D 1 to D N. It is connected to each input of the signal and also to the inverter circuit 6. The input H of the differential output type driver 5 is connected to the output of each of the differential input type receivers R 1 to RN . Further, the output G of the inverter circuit 6 is connected to the input of the enable signal of the differential output type driver 5. The outputs x 1 -x N and z 1 -z N of the differential output type drivers D 1 -D N are connected to the inputs of the differential input type receivers R 1 -RN and to the terminating resistor r, respectively.
このように接続された各部の動作を以下に説明
する。 The operation of each part connected in this way will be explained below.
差動入力型レシーバ３は、送受信制御部の出力
Ｘ，Ｚに差電圧が出力されたとき、出力Ｃに、送
受信制御部のTxD信号の論理値に対応した論理
値を出力する。一方、直流レベル検出回路４は、
入力Ａ，Ｂの差電圧が入力基準電圧信号REFよ
り高いとき、出力Ｆを論理値「１」の状態にし、
差電圧が入力基準電圧信号REFより低いとき、
出力Ｆを論理値「０」の状態にする。すなわち、
差動出力型ドライバ１の出力がイネーブル状態に
なつたとき、出力Ｆは論理値「１」、イネーブル
状態でないときは論理値「０」の状態となる。ま
たインバータ回路６の出力Ｇはこれを反転したも
のになるので、出力Ｆが論理値「１」のとき論理
値「０」となり、出力Ｆが論理値「０」のとき論
理値「１」となる。したがつて、インバータ６の
出力Ｇに接続された差動出力型ドライバ５は、差
動出力型ドライバ１，１′がイネーブル状態のと
き、イネーブル状態でない状態となり、差動出力
型ドライバ１，１′がイネーブル状態でないとき、
イネーブル状態となる。これにより、送受信制御
部の差動出力型ドライバ１，１′とこれに接続さ
れた拡張回路部の差動出力型ドライバ５が同時に
イネーブル状態になることを防止する。 The differential input type receiver 3 outputs a logic value corresponding to the logic value of the TxD signal of the transmission and reception control section to the output C when a differential voltage is output to the outputs X and Z of the transmission and reception control section. On the other hand, the DC level detection circuit 4 is
When the differential voltage between inputs A and B is higher than the input reference voltage signal REF, output F is set to a logic value "1",
When the differential voltage is lower than the input reference voltage signal REF,
The output F is set to the logic value "0". That is,
When the output of the differential output type driver 1 is enabled, the output F is a logic value "1", and when it is not enabled, the output F is a logic value "0". Also, the output G of the inverter circuit 6 is the inversion of this, so when the output F is a logic value "1", it becomes a logic value "0", and when the output F is a logic value "0", it becomes a logic value "1". Become. Therefore, the differential output type driver 5 connected to the output G of the inverter 6 is not enabled when the differential output type drivers 1 and 1' are enabled, and the differential output type drivers 1 and 1 are not enabled. ′ is not enabled,
It becomes enabled state. This prevents the differential output type drivers 1, 1' of the transmission/reception control section and the differential output type driver 5 of the expansion circuit section connected thereto from being enabled at the same time.
また、双方向信号線路L1〜LNに接続された差
動出力型ドライバD1〜DNは、出力Ｆにより、送
受信制御部の差動出力型ドライバ１，１′がイネ
ーブル状態のときのみ、イネーブル状態となる。
したがつて、双方向信号線路L1〜LNに接続され
た差動出力型ドライバD1〜DNは、送受信制御部
が送信可の状態のとき、TxD信号に対応した論
理値出力Ｃに対応する差電圧をx1〜xN，z1〜zNと
して出力する。 Furthermore, the differential output type drivers D 1 to D N connected to the bidirectional signal lines L 1 to L N are activated by the output F only when the differential output type drivers 1 and 1' of the transmission/reception control section are enabled. , becomes enabled.
Therefore, the differential output type drivers D 1 to D N connected to the bidirectional signal lines L 1 to L N output logic value output C corresponding to the TxD signal when the transmission/reception control unit is in the transmission enabled state. The corresponding differential voltages are output as x 1 to x N and z 1 to z N.
また、双方向信号線路L1〜LNに接続された差
動入力型レシーバR1〜RNの入力x1〜xN，z1〜zN
に入力される差電圧は、これに対応する論理値を
差動出力型ドライバ５の入力Ｈに出力され、この
差動出力型ドライバ５は、送受信制御部が送信可
でないとき、すなわち、TxE信号が論理値「０」
のとき、差電圧を出力し、拡張回路部のRxD信
号を送受信制御部に伝達する。 In addition, the inputs x 1 to x N , z 1 to z N of the differential input type receivers R 1 to R N connected to the bidirectional signal lines L 1 to L N
The differential voltage input to the TxE signal outputs the corresponding logical value to the input H of the differential output type driver 5, and this differential output type driver 5 outputs the TxE signal when the transmission/reception control section is not capable of transmitting. is logical value "0"
At this time, the differential voltage is output and the RxD signal of the expansion circuit section is transmitted to the transmission/reception control section.
本発明は以上説明したように、送受信制御部に
線路拡張回路を付加することによつて簡単に線路
を拡張を実現することができる。また、線路拡張
回路を付加しなければ、２つの双方向信号線路と
して使用できる。 As described above, according to the present invention, the line can be easily expanded by adding a line expansion circuit to the transmission/reception control section. Furthermore, without adding a line expansion circuit, it can be used as two bidirectional signal lines.
第１図は従来方式のブロツク図、第２図は本発
明の一実施例のブロツク図である。
１，１′……差動出力型ドライバ、２，２′……
差動入力型レシーバ、３，D1〜DN……差動出力
型ドライバ、５，R1〜RN……差動入力型レシー
バ、４……直流レベル検出回路、６……インバー
タ回路。
FIG. 1 is a block diagram of a conventional system, and FIG. 2 is a block diagram of an embodiment of the present invention. 1, 1'... Differential output type driver, 2, 2'...
Differential input type receiver, 3, D 1 -D N ... Differential output type driver, 5, R 1 - R N ... Differential input type receiver, 4 ... DC level detection circuit, 6 ... Inverter circuit.
Claims (1)
信号線に接続された第一のレシーバ回路と、前記
第一のレシーバ回路の出力に接続された複数の第
一のドライバ回路と、前記第一の信号線の差電圧
を検出し前記第一のドライバ回路にイネーブル信
号を与える検出回路と、前記第一のドライバ回路
に接続された信号線上の情報を受信する複数の第
二のレシーバ回路と、前記第二のレシーバ回路の
出力に接続され前記イネーブル信号を反転した信
号によつて制御されかつ前記双方向信号線の第二
の信号線に情報を送出する第二のドライバ回路と
を有することを特徴とする双方向信号線路拡張回
路。1 a first receiver circuit connected to a first signal line of at least two bidirectional signal lines; a plurality of first driver circuits connected to the output of the first receiver circuit; a detection circuit that detects a voltage difference between signal lines and provides an enable signal to the first driver circuit; and a plurality of second receiver circuits that receive information on signal lines connected to the first driver circuit. and a second driver circuit connected to the output of the second receiver circuit, controlled by a signal obtained by inverting the enable signal, and transmitting information to a second signal line of the bidirectional signal line. Features a bidirectional signal line expansion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12212083A JPS6014547A (en) | 1983-07-05 | 1983-07-05 | Extension circuit of bidirectional signal line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12212083A JPS6014547A (en) | 1983-07-05 | 1983-07-05 | Extension circuit of bidirectional signal line |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6014547A JPS6014547A (en) | 1985-01-25 |
| JPH035703B2 true JPH035703B2 (en) | 1991-01-28 |
Family
ID=14828114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12212083A Granted JPS6014547A (en) | 1983-07-05 | 1983-07-05 | Extension circuit of bidirectional signal line |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6014547A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7300045B2 (en) | 2004-09-28 | 2007-11-27 | Toshiba Tec Kabushiki Kaisha | Waiting tray for sheet processing tray |
| US8035424B2 (en) | 2007-02-14 | 2011-10-11 | Panasonic Corporation | AC-coupled interface circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5592057A (en) * | 1978-12-29 | 1980-07-12 | Fujitsu Ltd | Circuit for extending two-way transmission path |
| JPS56157153A (en) * | 1980-05-07 | 1981-12-04 | Casio Comput Co Ltd | Data repeating device |
| JPS5848547A (en) * | 1981-09-18 | 1983-03-22 | Toshiba Corp | Communication terminal branching system |
-
1983
- 1983-07-05 JP JP12212083A patent/JPS6014547A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6014547A (en) | 1985-01-25 |
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