JPH0357048A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To perform the relief of defective bit independently of inverted logic by selecting three or more memory cells where the same information is stored and outputting the output result of the majority of read-out data as output data. CONSTITUTION:Memory cell arrays 7a to 7c having the same constitution share a work line but have bit lines independently of one another. Memory cells 8 and Y selectors 9a to 9c which select bit lines are provided, and Y selectors 9a to 9c correspond to cell arrays 7a to 7c respectively. The same information is stored in three or more memory cells 8,and it is read out from these three memory cells 8, and output data is obtained from three or more output results by the majority decision. Thus, the relief of defective bit is possible independently of inversion from logical '1' is '0' or logical '0' to '1'.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Industrial application field B. Summary of the invention C. Prior art [Figure 4] D. Problems to be solved by the invention E. Means for solving problems F. Effect G, Examples [Figures 1 to 3] a. First embodiment [Fig. 1, Fig. 2 1 b. Second Embodiment [Figure 3 H6 Effects of the Invention (A. Field of Industrial Application) The present invention has a semiconductor memory, particularly a plurality of cell arrays,
The present invention relates to a semiconductor memory in which the same information is simultaneously input to each of the cell arrays and simultaneously outputted from each cell array, so that corresponding cells of the cell array compensate for failures of each other.

(B. Summary of the Invention) In the semiconductor memory described above, the present invention stores the same information in three or more memory cells in order to further improve reliability and reduce the defective rate, and when read out, the same information is stored in three or more memory cells. Output data is determined from among the above memory cells by majority vote, or cells that compensate for each other's defects are allocated to memory cells separated by a certain distance across two cell arrays.

+ (C. Prior Art) [Figure 1] In order to improve reliability in E2FROM, there are cases in which defective bits can be repaired using a double cell method. This double cell method means that two identical arrays are lined up, and when writing, the same information is written to both of them at the same time.
When writing to or reading from one cell array, the output signal is, for example, the AND of the signals output from the corresponding bit lines of the two cell arrays, and the corresponding cells of the two cell arrays mutually compensate for defects (destruction). It was designed to help each other.

FIG. 4 shows the two cell arrays. In the same figure, A. B is a cell array, and al and b1 and a2 and b2 are illustrated as cells that compensate each other.

Conventionally, as shown in FIG. 4, cells are arranged line-symmetrically about a center line C between two cell arrays A and B, and cells that compensate for each other (for example, a1
and bl, a2 and b2) were arranged so that their distances from the symmetry median line C were equal.

Here, the principle of this double cell system will be explained.

Assuming that the data of two cells that compensate each other are X1 and x2, the logical product x (=xl·x2) is taken as the data of that bit. Assuming that data reversal only occurs from O to 1 and that reversal from 1 to O never occurs, it is reasonable to treat it in this way.

When considering each case (1) to (4) organized in the table above, case (1) is normal, case (2) is defective in X2 but overall normal, and case (3) is defective in X1 but overall is normal. Normal, case (4) is defective in both xl and x2, and is defective as a whole.

This table is based on the assumption that the charge in the floating gate becomes O at most, but never reverses.When the charge is negative or 0, the logic is 1, and when the charge is positive, the logic is O. It is assumed that

According to this remedy, as in case (4), 2
If one cell is defective, it cannot be repaired, but in case (2)
), (3) where one of the cells is defective, it can be said that it can be repaired.

(D. Problems to be Solved by the Invention) By the way, it is said that if only one cell is defective, it can be repaired, but this only means that the data can be reversed from logic 0 to logic 1, but logic 1 This is the case assuming that the reversal from to logic O cannot occur. And, in fact, a reversal from a logic 1 to a logic O occurs less often than a reversal from a logic O to a logic 1 occurs. However, this does not mean that a failure that reverses from logic 1 to logic 0 will never occur. Furthermore, the double cell system is completely powerless against a failure that reverses from logic 1 to logic O.

In addition, the conventional double cell system, as shown in Figure 3,
Cells that compensate for each other are arranged symmetrically across the center line of symmetry C, so if a defect occurs near the boundary between the two memory cell arrays A and B (point d is where it occurs). Cells that compensate each other, e.g. a
There was a high possibility that both l and b1 would be defective. If cells that compensate for each other both become defective, relief is impossible.

The present invention has been made to solve these problems, and firstly, even if a logic reversal occurs from logic 1 to O, conversely, even if a logic reversal occurs from logic O to 1, there is no relief. The second purpose is to prevent cells that compensate each other from both becoming defective.

(E. Means for Solving Problems) In order to solve the above problems, the semiconductor memory of the present invention stores the same information in three or more memory cells, and when it is read out, the same information is stored in three or more memory cells. It is characterized in that output data is determined by majority vote from among them.

A second semiconductor memory of the present invention is characterized in that cells that compensate for each other's defects are allocated to memory cells separated by a certain distance across a plurality of cell arrays.

(F. Effects) According to the first semiconductor memory of the present invention, the same information is stored in three or more memory cells, read from the three memory cells, and output data is obtained by majority vote from the three or more output results. Therefore, relief is possible regardless of whether the reversal is from logic 1 to O or from logic O to 1.

According to the second semiconductor memory of the present invention, the cells that compensate each other are not arranged symmetrically about the center line between the two cell arrays, but are arranged at the same distance apart from each other. , the probability of both being defective is low unless the defective location is extremely large. Therefore, even if a defect occurs, there is a high possibility that it will be compensated, so that the defect rate can be substantially reduced.

(G. Embodiment) [FIGS. 1 to 3] The semiconductor memory of the present invention will be described in detail below according to the illustrated embodiment.

(a. First Embodiment) [Fig. 1, Fig. 2 1 Fig. 1 and Fig. 2 show one embodiment in which the present invention is applied to an E'' PROM, and Fig. 1 shows the whole. FIG. 2 is a circuit diagram of the majority circuit.

In the drawing, 1 and 2 are address buffers, 3 and 4 are address row decoders, and 5 and 6 are high voltage level conversion circuits that convert the output signals of the row decoders 3 and 4 to high voltage levels.

7a, 7b, and 7c are memory cell arrays having exactly the same configuration. The memory cell arrays 7a, 7b, and 7c share a word line, but each independently owns a bit line.

8, 8, 8, . . . are memory cells, 9a, 9b, 9C are Y selectors for selecting bit lines, Y selector 8a corresponds to cell array 7a, and Y selector 8b corresponds to cell array 7.
b, and the Y selector 9C corresponds to the cell array 7C. 10a, 10b, and 10c are sense amplifier/write circuit groups, the sense amplifier/write circuit group 10a corresponds to the Y selector 9a, and the sense amplifier/write circuit group 10b corresponds to the Y selector 9a.
Corresponding to selector 9b, sensor/write circuit group 10c
corresponds to Y selector 9C. One sense amplifier is provided corresponding to each bit line. Furthermore, one write circuit is provided corresponding to each bit line.

Therefore, in the case of a memory having an 8-bit per word structure, there are 24 sense amplifiers and 24 write circuits.

11 is a buffer circuit, and there are eight combinations of an input buffer section (simply indicated as a human power section in the drawing) and an output buffer section (simply indicated as an output section in the drawing). The respective cover sections include sense amplifier/write circuits 10a, 10b. 10c
transmits the input data signal to the

Further, each output buffer section receives an output data signal from one sense amplifier of the sense amplifier/write circuit group 10a,
The output data signal from the sense amplifier corresponding to the sense amplifier of the sense amplifier/write circuit 10b and the sense amplifier . Write circuit group 1. It has a built-in majority circuit shown in FIG. 2 which receives the output data signals from the sense amplifiers of the Oc and the corresponding sense amplifiers, takes a majority vote, and outputs the result as data. This majority circuit will be explained later.

12 indicates the control circuit that controls the entire E" PROM.
, , Receives a chip enable signal, an output enable signal, and a write enable signal. Reference numeral 13 indicates timer 7, and this evening/timer 13 controls the evening/timing of the start and end of writing. A clock generator 14 generates a clock in response to a signal from the timer 13. 15
is a booster circuit that boosts the clock pulses generated from the clock generator 14, and the program voltage Vpp obtained from the booster circuit 15 is applied to the sense amplifier/write circuit group 1.
0a, 10b, 10c and high voltage level conversion circuit 5
, 6. l6 is a high voltage control circuit.

Next, the majority circuit shown in FIG. 2 built in each output buffer section of the buffer circuit 1l will be explained.

The majority circuit calculates the exclusive OR of signals A and B (A-B+
B-A), an exclusive OR circuit EXOR which obtains the AND of the output signal of the exclusive OR circuit EXOR and signal C, and a first AND circuit ANDI which obtains the AND of the signals A and B. The second AND circuit AND2 and the first AND circuit AN
The output signal of DI and the second AND circuit A. It consists of a logical sum circuit OR which obtains a logical sum with the output signal of N D 2.

The formula for the logical operation performed by the majority circuit is as follows.

F (A.B, C) = (A-B+A-B) ・C+
A-B where signal A%B. If C is equal to each other, (1)
If (2) is the case where B and C are equal and A is different, (3) is the case where A and C are equal and B is different, and (4) is the case where A and B are equal and C is different, then the output F in each case is The relationship between the majority and the majority is shown in the table below.

Table As is clear from this table, the calculation result and the majority match.

Therefore, it is clear that it is possible to output by taking a majority vote among the output results of three memory cells, and even if there is a defect that reverses from logic 0 to logic 1, there is a defect that reverses from logic 1 to logic O. Even if there are defects, the bit data will be compensated as long as the number of defects does not exceed the majority.

In this E2FROM, when writing signals, the same signals are simultaneously written to the cell arrays 7a, 7b, and 7c. When reading a signal, the signal A output from the cell array 7a is amplified by the sense amplifier in the sense amplifier/write circuit group 10a, and the signal B output from the cell array 7b is amplified by the sense amplifier in the sense amplifier/write circuit group lb. The signal C that is amplified by the sense amplifier and output from the cell array 7C is amplified by the sense amplifier in the sense amplifier/write circuit group 10c, and then sent to the cell array 7a by the majority circuit in the output buffer section of the buffer circuit 11.
A majority vote of the signals from 7b and 7c is taken and this is sent to the outside as an output data signal. Therefore, even if a defect occurs in one cell of cell array 7a, the defect in that cell is compensated for by the cells corresponding to the defective cell in cell arrays 7b and 7c on the principle of majority voting. Since data can be compensated as long as the number of defective cells does not exceed the majority of cells that compensate each other, reliability can be significantly improved.

In the above embodiment, three or more unit cells are allocated to one bit, but if the number is odd, a larger number of unit cells may be allocated to one bit.

In this embodiment, the present invention is applied to an E2PROM, but the present invention is not necessarily limited to this, and the present invention can be applied to other semiconductor memories such as an EPROM and an SRAM.

(b. Second Embodiment) [FIG. 3] FIG. 3 is an overall block diagram showing a second embodiment of the semiconductor memory of the present invention. This example also applies the present invention to an E”PROM.
It was applied to

This semiconductor memory has only two cell arrays 7a and 7b, and two signals A. H's logic IJI (
Or logical sum) and get it A-B (or A + B
) is different from the first embodiment in that the second embodiment outputs the following, but the other points are the same, and since the common points have already been explained, the explanation will be omitted.

This semiconductor memory differs from the conventional double cell system (see Figure 4) in that the cells are arranged so that the interval β between cells that compensate for each other is equal for all bears (for example, 8a and 8b, 8C and 8d). They are different in that they are Therefore, even if a defect occurs in the vicinity of the boundary between the two cell arrays 7a and 7b, there is no risk that cells that compensate for each other will both become defective, and compensation is possible.

Therefore, it is possible to substantially reduce the defect rate.

It should be noted that if the defect rate is to be reduced by keeping the distance between the cells that compensate each other constant, the third technique is
The present invention can be applied not only to a double cell type semiconductor memory as shown in the figure, but also to a so-called triple cell type semiconductor memory as shown in FIG. In fact, this technical idea is also implemented in the embodiment shown in FIG.

(H. Effects of the Invention) As described above, the first semiconductor memory of the present invention stores the same information in three or more memory cells, and when reading out the same information, the three or more memory cells store the same information. is selected, and the output result with the largest number of the read data is set as the output data.

Therefore, according to the first semiconductor memory of the present invention, the same information is stored in three or more memory cells, the three memory cells are also read, and the output data is determined by majority vote from the output results of the three or more read outputs. Therefore, relief is possible regardless of whether the reversal is from logical 1 to O or from logical O to O.

A second semiconductor memory of the present invention has a plurality of cell arrays, and the same information is simultaneously input to each of the cell arrays and outputted from each at the same time, so that corresponding cells of the cell array can compensate for failures. This semiconductor memory is characterized in that cells that compensate for each other's defects are allocated to memory cells spaced a certain distance across a plurality of cell arrays.

According to the second semiconductor memory of the present invention, cells that compensate for each other are not arranged symmetrically about the center line between two cell arrays, but are all arranged at the same distance apart, so that defects can occur. Unless the parts are very large, the probability of both being defective is low. Therefore, since it is possible to compensate even if a defect occurs, it is possible to substantially reduce the defect rate.

[Brief explanation of drawings]

1 and 2 are for explaining one embodiment of the semiconductor memory of the present invention, and FIG. 1 is an overall block diagram,
FIG. 2 is a circuit diagram showing a majority circuit, FIG. 3 is an overall block diagram showing a second embodiment of the semiconductor memory of the present invention, and FIG.
The figure is a block diagram showing the main parts of a conventional example. Explanation of symbols 7a, 7b, 7c...Cell array, 8...Cell, 8a, 8b...Cells that compensate for each other, 8c, 8d...Cells that compensate for each other, C.Cells that compensate for each other distance between.

Claims (2)

[Claims] (1) The same information is stored in three or more memory cells, and when reading out, the three or more memory cells that have stored the same information are selected, and the output result with the largest number of the read data is set as the output data. A semiconductor memory characterized by (2) Semiconductor memory that has multiple cell arrays, and by simultaneously inputting the same information to each of the cell arrays and outputting the same information from each at the same time, the corresponding cells in the cell array compensate for each other's failures. A semiconductor memory characterized in that a pair of cells that compensate for each other's defects are assigned to memory cells separated by a certain distance across a plurality of cell arrays.