JPH0357499B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vector instruction processing device, and more particularly to a vector instruction processing device that controls the execution of vector operations using mask bits for each vector element.

[Conventional technology]

In order to improve the processing power of vector processors, conventional vector instruction processing devices
It is necessary to process a wider range of types of processing at high speed, especially IF in FORTRAN programs.
The challenge has been how to process DO loops containing statements at high speed, and methods have long been devised to control and process operations using mask vectors.

To briefly explain the concept of the processing process using the mask vector in the DO loop with reference to Figure 2, this DO loop uses the vector operand C(I)
The vector elements of vector operand C(I) and vector operand C(I) are compared, and the vector element of vector operand C(I) that is smaller than the value of vector operand D(I) is divided into vector operand A(I), This is an example of repeating processing for N sets of vector elements to replace them with the addition result of corresponding vector elements of B(I).

First, the vector operands C(I) and D(I) are compared for each vector element correspondence, and if C(I)>D(I), it is "0", and if C(I)<D(I), it is "0". creates a bit string indicating the value "1". This bit string is a mask vector, and each bit is called a mask bit. Then, according to this created mask vector, the vector elements of vector operands A(I) and B(I) corresponding to the mask bit whose value is "1" are added together, and the result is converted into C(I). write to the corresponding vector element of . Other vector operands C(I), that is, vector elements of vector operand C(I) corresponding to mask bits whose value is "0" are not changed.

Arithmetic processing using mask vectors is performed in the above manner. When creating mask vectors, by preparing multiple sets of comparators of the same type, the comparators can be sequentially processed at high speed. It is possible to create one. Therefore, in order to process vector calculations using mask vectors at high speed, it is important to process mask vectors that are sequentially created in batches at high speed and perform calculation processing.

For this reason, the conventional vector instruction processing device reads only the valid vector elements indicated by the mask bits at the time of requesting a vector element read request, as shown in FIG. 3, and the operation is suppressed. There is a vector instruction processing device that skips invalid operations by inhibiting reading of vector elements.

In this conventional vector instruction processing device, a mask vector consisting of a number of mask bit strings corresponding to the number of vector elements to be processed is divided into certain processing units.
Mask vectors (hereinafter referred to as mask vector data) divided into fixed processing units are treated as one processing unit, and processing is sequentially performed at high speed. To this end, mask vectors that are sequentially created in batches are temporarily stored in a storage device prior to arithmetic processing using mask vectors. When the storage of the mask vector in the storage device is completed, or in parallel with the storage operation, an instruction to start arithmetic processing using the mask vector is issued to the vector instruction processing device. When the vector instruction processing device receives this instruction, it first reads the vector operand addresses (VH
1, 2 and VH3) in vector address registers 51, 52 and 53, respectively.
Vector element distances (VI1, 2, and 3) corresponding to operands 1, 2, and 3 are initialized in vector element distance registers 54, 55, and 56, respectively. The control device 20 issues a command to the mask vector data reading unit 30 to cause the mask vector data reading unit 30 to issue a request to the storage device 10 to read mask vector data. mask vector
Upon receiving the data read request, the storage device 10 reads the corresponding mask vector data and sends it to the mask vector data processing section 40. Mask vector data processing section 40
In , processing is performed based on mask vector data.

FIG. 4 shows the process of processing mask vector data and the procedure for generating addresses of vector elements corresponding to operation instruction bits. Within one vector instruction, adding a constant vector element distance (VIi) to the vector operand address (VHi) yields the vector operand address of the next vector element. Here, referring to FIG. 4a, the value of the read mask vector data of bit length (n+1) is the operation instruction bit "3rd bit, 8th bit, ..., (n-3)th bit". 1” (the number is m)
The case where all other (n-m+1) bits indicate the operation inhibit bit "0" is shown. The vector operand address (VHi, ₀ ) is the address of the vector element corresponding to the 0th bit of the mask vector data.
At this time, the address of the vector element corresponding to the 3rd bit of the mask vector data (VHi, ₃ )
is obtained by VHi, ₃ = VHi, ₀ + 3 × VIi. Here, the multiplier 3 of the distance between vector elements (VIi) is the operation suppression bit "0" until the first operation instruction bit "1" is found from the beginning (0th bit) of the mask vector data in Figure 4a. It can be found by counting the number of .
Furthermore, in order to obtain the address (VHi, ₈ ) of the vector element corresponding to the 8th bit of the mask vector data to be calculated next, as shown in FIG. 4b, the mask vector data in FIG. - Shift the vector data to the left by 3 bits corresponding to the multiplier, and accordingly invert the 3rd bit, the operation instruction bit "1", to use as mask vector data to be used next. At this time, a logic level "1" is input to the shift-in. The thus obtained mask vector data of FIG. A multiplier of 5 is obtained, and the fourth
The address (VHi, ₈ ) of the vector element corresponding to the 8th bit in Figure a is obtained by VHi, ₈ = VHi, ₃ + 5 x VIi.

By repeating the above operation m times, the operation instruction bit "1" of the (n-3)th bit in FIG. 4a, as shown in FIG. 4c, is inverted and shifted to the first bit position. mask vector data is obtained. The address of the vector element obtained by performing the same operation once again on the mask vector data in Figure 4c and using the multiplier 4 (VHi, ₀ ') VHi, ₀ '=VHi, _o-3 +4×VIi is the address of the vector element corresponding to the first bit of the next consecutive new mask vector data.

The above operations are repeated until the multipliers obtained in each operation are added each time, and the resulting added value matches the bit length (n+1) of the read mask vector data. When a match is detected, , ends the processing of one mask vector data.

Referring again to FIG. mask vector
The data processing unit 40 receives the mask and
As described above, the vector data is counted by counting the number of operation inhibit bits ``0'' until the operation instruction bit ``1'' is found, and the obtained value is used as a multiplier of the vector element distance VIi to be used in the address generation section. 50. The multiplier for the inter-vector element distance VIi sent to the address generation unit 50 is determined by the multiplier 57.
An address difference is generated and sent to the address adder 58. The address adder 58 adds the address difference generated by the multiplier 57 and the vector operand address VHi of the corresponding vector operand selected by the selector S54 to obtain the address of the vector element to be operated on. is obtained, and an operand request for vector elements is sent to the storage device 10. At the same time, selector S51,5
The value of the vector address register (51, 52 or 53) of the corresponding vector operand is updated through either selector 2 or 53. When the storage device 10 receives an operand request for a vector element, in the case of a read request, the storage device 10 reads the corresponding vector element and sends it to the arithmetic unit 60 . Distance between one vector element
When the operand requests for the vector elements corresponding to operands 1, 2, and 3 have been sent to the storage device 10 for the multiplier of VIi, the new multiplier for the distance between vector elements VIi becomes the mask vector data. It is supplied from the processing section 40 to the address generation section 50. Mask vector data processing section 4
When it is detected that the multiplier of the vector element distance VIi generated at 0 corresponds to the distance to the first bit position of the next consecutive mask vector data, it is reported to the control device 20, and the above is performed. The series of operations ends. generated by the multiplier of the vector element distance VIi corresponding to the distance to the first bit position of the next consecutive mask vector data sent to the address generation unit 50.
The address of the vector element is not used as an operand request to the storage device 10 by command of the control device 20, but is used as a vector address.
It is used only for the purpose of updating the value of the register (51, 52 or 53) to the address of the vector element corresponding to the first bit position of the next consecutive mask vector data.

In parallel with this operation, the control device 20 sends a command to the mask vector data reading unit 30 to read out the next consecutive mask vector data to execute sequential processing, and continues processing. Start.

[Problem that the invention seeks to solve]

The conventional vector instruction processing device described above has a mask vector data processing section that processes one mask vector instruction.
After waiting for vector data processing to finish, new mask vector data to be processed next is fetched from storage. Therefore,
The mask vector data processing unit retrieves the mask vector data from the storage device and processes the mask vector data.
The data has to wait without being processed until it is sent to the vector data processing unit, and as a result, the processing in the arithmetic unit has idle time during which processing cannot be performed, resulting in a significant drop in performance due to the wait time for accessing the storage device. It has the disadvantage of becoming.

[Means for solving problems]

According to the present invention, there is provided a storage device for storing mask vectors composed of a plurality of mask bit strings, and mask vector data obtained by dividing the mask vectors into fixed processing units, which are sequentially batched as processing units. a mask vector data processing unit for processing the mask vector data, and a mask vector data reading unit for reading the mask vector data from the storage device, and executes vector operations using mask bits for each vector element. In the data processing device to be controlled, a mask vector data address register that holds the address of the mask vector data that is sequentially processed, and a mask vector data that holds the read data width value of the mask vector data. creating an address of preceding mask vector data to be sequentially processed on the storage device from a read data width register and the mask vector data address and the read data width value of the mask vector data; an address adder, from the storage device to the mask vector;
the mask vector data reading unit for sequentially pre-fetching data; and the mask vector data buffer for storing the sequentially pre-fetched mask vector data;
The mask vector data processing section
When vector data is required, the corresponding mask vector data is transferred from the mask vector data buffer to the mask vector data buffer.
A vector instruction processing device is obtained, characterized in that the vector instruction processing device is supplied to a data processing section.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a vector instruction processing device which is an embodiment of the present invention. In FIG. 1, this embodiment uses a storage device 10 that stores mask vectors composed of a plurality of mask bit strings as sets of mask vector data divided into fixed processing units.
and a mask for storing the mask vector data fetched in advance from the storage device 10 one after another.
It includes a vector data buffer 11, a mask vector data reading section 30a that reads out the mask vector data, and a mask vector data processing section 40 that processes the mask vector data all at once.

The storage device 10 stores mask vectors composed of a plurality of mask vector data, vector elements of a plurality of vector operands, and the like. Mask vector data buffer 1
1 is a dedicated data buffer that holds a plurality of mask vector data. The mask vector data processing section 30a is a mask vector data reading section for reading out preceding mask vector data that is sequentially processed,
Selector S30 and mask vector data holding the address of the mask vector data.
Address register 31 and mask vector
a mask vector data read data width register (hereinafter abbreviated as read data width register) 32 that holds a read data width value of data;
Mask vector data address register 3
The address adder 33 adds the output signal of 1 and the output signal of the read data width register 32.

Furthermore, this embodiment includes an arithmetic unit 60 connected to the storage device 10, an address generation unit 50 connected to the mask vector data processing unit 40, and a read pointer (hereinafter referred to as mask) of the mask vector data buffer 11.・Vector data pointer) 70, and a control device 20 that controls these and each part.

When this embodiment receives an instruction to start arithmetic processing using a mask vector, it sets initial values,
Mask vector data address register 3
1 is set to the address corresponding to the first mask vector data to be processed through the selector S30, and the read data width register 32 is set to the initial addition value "0". At the same time as the initial value is set, the address adder 33 adds the initial value of the mask vector data address register 31 and the initial added value "0" of the read data width register 32 according to a command from the control device 20.
The address of the first mask vector data to be processed is generated, and a request to read the mask vector data is issued to the storage device 10. At this time, the control device 20 simultaneously sets the read data width value of the mask vector data in the read data width register 32. Thereafter, the read data width register 32 holds the read data width value of the mask vector data.
The read data width value of this mask vector data can be arbitrarily set to correspond to the length of one data read from the storage device 10, unique to each vector instruction processing device.

Upon receiving the mask vector data read request, the storage device 10 reads the target mask vector data from the corresponding address and sends it to the mask vector data buffer 11. The mask vector data buffer 11 holds the mask vector data until the mask vector data processing section 40 uses it.

In this way, the present embodiment completes the fetch operation of the first mask vector data to be processed. Originally, the mask vector was stored in storage 10
The mask vector data is stored consecutively on the top, and the mask vector data is divided into certain processing units, and the size of the certain processing unit is determined by the read data width value of the mask vector data. It can be made to correspond. Therefore, by sequentially adding the read data width value of the mask vector data to the address of one mask vector data, the address of the preceding mask vector data can be generated. When a request to read the first mask vector data to be processed is issued, the control device 20 subsequently registers the mask vector data address register 31 in order to read new consecutive mask vector data from the storage device 10. address adder 3 and the read data width value of the mask vector data held in the read data width register 32.
3, the address of new continuous mask vector data is generated, and a read request for new continuous mask vector data is sent to the storage device 10. At the same time, the control device 20 updates the value of the mask vector data address register 31 through the selector S30.

By repeating this operation, the mask vector data to be sequentially processed is fetched, and before the mask vector data processing unit 40 issues a request to use the mask vector data, the mask vector data A plurality of mask vector data are stored in the buffer 11. In the mask vector data processing section 40, when mask vector data is required for processing the mask vector data, the control device 2
Issue a request for mask vector data to 0. Upon receiving this request, the control device 20 retrieves the stored mask vector data from the corresponding position in the mask vector data buffer 11 indicated by the mask vector data pointer 70.
The data is supplied to the mask vector data processing section 40.

After supplying the corresponding mask vector data, the control device 20 supplies the mask vector data.
The value of pointer 70 is masked, vector data,
The mask vector data stored in the buffer 11 is updated to point to the mask vector data to be used next.

The mask vector data supplied to the mask vector data processing unit 40 is converted into an operation instruction bit “1” by counting the number of operation inhibit bits “0” in the mask vector data processing unit 40. A process is performed to calculate the multiplier of the distance VIi between vector elements in order to generate only the address of the vector element for which execution of the corresponding operation is instructed, and the following operation is described in the description of the conventional technology. Since the operation is the same as that of the first embodiment and is not the gist of the present invention, the explanation will be kept brief.

The multiplier of the vector element distance VIi calculated by the mask vector data processing unit 40 is sent to the address generation unit 50, which generates the address of the target vector element and sends an operand request to the storage device 10. Sent out. Storage device 1
0 reads the corresponding vector element and sends it to the arithmetic unit 60. The arithmetic device 60 stores the arithmetic result in the corresponding location on the storage device 10 corresponding to the operand request issued in advance.

In the above operation, the control device 20 performs the preceding fetch of mask vector data and the mask vector data.
It controls the supply of mask vector data to the vector data processing unit 40 and the sending of operand requests for vector elements instructed to execute operations to the storage device 10 so that they are performed independently and in parallel, and also controls the operation results. storage device 1
The storage to 0 is also controlled to be performed independently of these three operations.

〔Effect of the invention〕

As explained above, the present invention creates the address of preceding mask vector data to be sequentially processed from the address of the mask vector data and the read data width value of the mask vector data, and Before the vector data processing unit needs the mask vector data, the mask vector data is fetched one after another, stored in a dedicated mask vector data buffer, and then processed. To enable high-speed supply of corresponding mask vector data from a mask vector data buffer to a mask vector data processing section when the section requires the mask vector data. As a result, the mask vector
This has the effect that play due to mask vector data waiting time in the data processing section can be minimized, and high-speed continuous processing of mask vector data becomes possible. Additionally, the idle time due to vector element waiting time in the arithmetic unit can be significantly reduced, thereby making it possible to further improve the usage efficiency of the arithmetic unit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 shows an example of a FORTRAN program whose calculations are controlled and processed by mask vectors, Figure 3 is a block diagram showing a conventional device, and Figure 4 shows the mask vector data processing process and calculations. FIG. 7 is a diagram showing a procedure for generating addresses of vector elements corresponding to instruction bits. 10...Storage device, 11...Mask vector data buffer, 20...Control device, 30
a...Mask vector data reading section, 4
0...Mask vector data processing unit, 50...
...address generation unit, 60... arithmetic unit, 70...
Mask vector data read pointer, 3
1...Mask vector data address register, 32...Mask vector data read data width register, 51, 52, 53...Vector address register, 54, 55, 56...
Vector element distance register, 33, 58... Address adder, 57... Multiplier, S30, S5
0, S51, S52, S53, S54...Selector.

Claims (1)

[Claims] 1. A storage device that stores mask vectors composed of a plurality of mask bit strings, and a mask vector that sequentially processes mask vector data in which the mask vectors are divided into fixed processing units as processing units. A data processing device that includes a vector data processing unit and a mask vector data reading unit that reads the mask vector data from the storage device, and controls execution of vector operations using mask bits for each vector element. a mask vector data address register that holds the address of the mask vector data to be processed sequentially;
A mask vector data read data width register holding a read data width value of vector data, and a mask vector data address and a read data width value of mask vector data sequentially processed onto the storage device. the mask vector data readout section, which has an address adder for creating an address of the preceding mask vector data to be read, and fetches the mask vector data one after another from the storage device; and a mask vector data buffer for storing previously fetched mask vector data, and when the mask vector data processing section requires mask vector data, the mask vector data buffer is stored. A vector instruction processing device characterized in that the mask vector data is supplied from a buffer to the mask vector data processing section.