JPH0357548B2 - - Google Patents

Info

Publication number
JPH0357548B2
JPH0357548B2 JP56212982A JP21298281A JPH0357548B2 JP H0357548 B2 JPH0357548 B2 JP H0357548B2 JP 56212982 A JP56212982 A JP 56212982A JP 21298281 A JP21298281 A JP 21298281A JP H0357548 B2 JPH0357548 B2 JP H0357548B2
Authority
JP
Japan
Prior art keywords
signal
recording medium
speed
reset
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56212982A
Other languages
Japanese (ja)
Other versions
JPS58114356A (en
Inventor
Takashi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56212982A priority Critical patent/JPS58114356A/en
Publication of JPS58114356A publication Critical patent/JPS58114356A/en
Publication of JPH0357548B2 publication Critical patent/JPH0357548B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Rotational Drive Of Disk (AREA)
  • Control Of Velocity Or Acceleration (AREA)
  • Control Of Electric Motors In General (AREA)

Description

【発明の詳細な説明】 この発明は主としてデジタル信号が同心円状ま
たはスパイラルに線速度一定で記録された回転円
盤を記録媒体とする再生機の速度制御装置の改良
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention mainly relates to an improvement in a speed control device for a reproducing machine whose recording medium is a rotating disk on which digital signals are recorded concentrically or spirally at a constant linear velocity.

第1図はこの種の装置の一例である。 FIG. 1 shows an example of this type of device.

図において1はビツト周期T0最長反転間隔
Tmax(Tmax=11×T0)なるデジタル信号が一
定の線速度Vでスパイラルに記録された円盤、2
は記録されたデジタル信号を円盤1より読み取り
更に電気信号である再生信号に変換するピツクア
ツプ(以後PUとする)、3はPU2の半径位置
(半径ir)を示す位置信号を出力する位置検出器、
4は円盤1の1回転当りNコのパルスを出力する
パルス発生器、5は上記位置信号より周波数F1
が次式で与えられる基準サーボ信号を出力する演
算器。
In the figure, 1 is the bit period T 0 longest inversion interval
A disk on which a digital signal Tmax (Tmax=11×T 0 ) is recorded spirally at a constant linear velocity V, 2
3 is a pick-up (hereinafter referred to as PU) that reads a recorded digital signal from disk 1 and converts it into a playback signal that is an electric signal; 3 is a position detector that outputs a position signal indicating the radial position (radius IR) of PU 2;
4 is a pulse generator that outputs N pulses per rotation of disk 1, and 5 is a frequency F 1 based on the above position signal.
A computing unit that outputs a reference servo signal given by the following formula.

F1=V×N/2π×r ……(1) 6は基準サーボ信号とパルスの位相差を比較す
る位相比較器、7は増巾器、8はモータである。
F 1 =V×N/2π×r (1) 6 is a phase comparator that compares the phase difference between the reference servo signal and the pulse, 7 is an amplifier, and 8 is a motor.

パルス発生器4の出力パルスは1式で与えられ
る周波数F1の基準サーボ信号を基準として、パ
ルス発生器4、位相比較器6、増巾器7、モータ
8なる位相同期系を形成している。即ち、パルス
の周波数F2はF1と同一である。
The output pulses of the pulse generator 4 form a phase synchronized system consisting of the pulse generator 4, phase comparator 6, amplifier 7, and motor 8, with reference to a reference servo signal of frequency F 1 given by one set. . That is, the pulse frequency F 2 is the same as F 1 .

第1図においてPU2に対する円盤1の相対線
速度V′は次式で与えられる。
In FIG. 1, the relative linear velocity V' of the disk 1 with respect to the PU 2 is given by the following equation.

V′=2πr×F2/N =2πr×F1/N(∴F1=F2) =2πrVN/2πrN(∵(1)式より) =V 即ち、記録時と同一の線速度一定で信号が再生
できる。
V ' = 2πr can be played.

しかし、記録時のデジタル信号は同一であつて
も記録線速度VがV+ΔVとなつた場合には再生
される信号のビツト周期T0′は T0′=T0×V/V+ΔV≠T0(ΔV≠0) となり正しく再生できないという欠点が第1図の
方式にはある。
However, even if the digital signal during recording is the same, when the recording linear velocity V becomes V+ΔV, the bit period T 0 ' of the reproduced signal becomes T 0 '=T 0 ×V/V+ΔV≠T 0 ( The method shown in FIG. 1 has the disadvantage that it cannot be reproduced correctly because ΔV≠0).

この発明は上記従来方式の欠点を解消すべく再
生信号のビツト周期T0′とT0となるべく再生信号
より直接的に円盤1の回転速度等を制御しようと
するものである。
In order to eliminate the drawbacks of the conventional system, the present invention attempts to control the rotational speed of the disk 1 as directly as possible from the reproduction signal so that the bit periods T 0 ' and T 0 of the reproduction signal can be adjusted.

以下この発明の実施例を図に示し説明する。第
2図はこの発明の一実施例であり、10,11は
夫々再生信号の立ち上り及び立下り時にリセツト
信号を出力する第1及び第2のゼロクロス検出
器、12,13は夫々第1及び第2のゼロクロス
検出器10,11からのリセツト信号によりリセ
ツトされ時間と共に出力電圧が上昇する第1及び
第2のランプ(ramp)発生器、14は2つの入
力の内大なる方を出力する比較器、15は比較器
14の出力のピーク値を保持し時定数τ0で降下す
る速度信号を出力するピークホールド回路、16
は速度信号と基準電圧との誤差を出力する差動増
巾器、17は基準電圧源である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows an embodiment of the present invention, in which 10 and 11 are first and second zero-cross detectors that output reset signals at the rise and fall of the reproduced signal, respectively, and 12 and 13 are first and second zero-cross detectors, respectively. 14 is a comparator that outputs the larger of the two inputs; first and second ramp generators that are reset by reset signals from the zero-cross detectors 10 and 11 of 2 and whose output voltage increases over time; , 15 is a peak hold circuit that holds the peak value of the output of the comparator 14 and outputs a speed signal that drops with a time constant τ 0 ; 16
1 is a differential amplifier that outputs the error between the speed signal and the reference voltage, and 17 is a reference voltage source.

また、デジタル信号中には一定周期毎にTmax
が2回連続して挿入されているものとする。
Also, during digital signals, Tmax is
Assume that the is inserted twice consecutively.

第2図の動作を以下に図により説明する。 The operation of FIG. 2 will be explained below with reference to the drawings.

第3図は安定回転時の第2図各部の電圧波形で
あり、Aは再生信号、BCは夫々第1及び第2の
ゼロクロス検出器10,11からのリセツト信
号、DEは夫々第1及び第2のランプ発生器12,
13の出力波形、Fは比較器14出力、Gは速度
信号である。
FIG. 3 shows voltage waveforms at various parts in FIG. 2 during stable rotation, where A is a reproduction signal, BC is a reset signal from the first and second zero cross detectors 10 and 11, respectively, and DE is a reset signal from the first and second zero cross detectors 10 and 11, respectively. 2 lamp generators 12,
13, F is the output of the comparator 14, and G is the speed signal.

第3図はほぼ正規の速度で信号が再生されてい
る状態を示しているが、モータ8即ち円盤1の回
転の立ち上り時等には第3図に示した再生信号A
及びリセツト信号BCは時間軸方向に伸びた波形
となつている。ランプ発生器12,13の電圧上
昇速度は一定である。このため第3図のDEFの
各波形のピーク値はこの図と比べて上昇し速度信
号Gの電圧も上昇したものとなる。これに伴い差
動増巾器16及び増巾器7の出力も上昇する。こ
のためモータ8の速度も上昇する。
FIG. 3 shows a state in which the signal is being reproduced at an approximately normal speed, but at the start of rotation of the motor 8, that is, the disk 1, the reproduction signal A shown in FIG.
The reset signal BC has a waveform extending in the time axis direction. The rate of voltage rise of the ramp generators 12, 13 is constant. Therefore, the peak values of each waveform of DEF in FIG. 3 are increased compared to this diagram, and the voltage of the speed signal G is also increased. Along with this, the outputs of the differential amplifier 16 and the amplifier 7 also increase. Therefore, the speed of the motor 8 also increases.

逆にPU2の位置が急に内周から外周に移動し
た場合(半径rの値が急増した場合)等において
は記録信号の再生速度が第3図に示した正規の場
合と比べて高くなつている。このため前述の場合
とは逆に再生信号A及びリセツト信号BCは第3
図の場合と比べ時間軸方向につまつたものとな
る。このため第3図DEFの各波形のピーク値は
低下し速度信号Gの電圧も低下する。これに伴い
モータ8印加電圧が低下し回転も低下する。
Conversely, when the position of PU2 suddenly moves from the inner circumference to the outer circumference (when the value of radius r increases rapidly), the playback speed of the recorded signal becomes higher than in the normal case shown in Figure 3. There is. Therefore, contrary to the above case, the reproduction signal A and the reset signal BC are
Compared to the case shown in the figure, the time axis is condensed. Therefore, the peak value of each waveform in FIG. 3 DEF decreases, and the voltage of the speed signal G also decreases. Accordingly, the voltage applied to the motor 8 decreases, and the rotation also decreases.

以上述べた如く第2図及び第3図に示した実施
例によれば、記録時の線速度Vがある幅を持つて
選択できる場合にも線速度Vに依存せずにほぼ正
規の線速度で信号を再生できる。加えて、第1図
に示した方式と比べ、比較的高い機械精度を要す
る位置検出器3を必要としないという特長がうま
れる。
As described above, according to the embodiment shown in FIGS. 2 and 3, even when the linear velocity V during recording can be selected within a certain range, the linear velocity is almost normal regardless of the linear velocity V. You can play the signal with In addition, compared to the method shown in FIG. 1, this method has the advantage that it does not require the position detector 3, which requires relatively high mechanical precision.

なお第3図DEFGの各波形をデジタルの数値と
考えると、ランプ発生器10,11はカウンタに
よつても構成できる。
Note that if each waveform in FIG. 3 DEFG is considered to be a digital value, the ramp generators 10 and 11 can also be configured by counters.

又、上記説明は円盤状のものについて述べた
が、テープについてもキヤプスタンモータ等に対
し実施できる。
Further, although the above description has been made regarding a disk-shaped one, the tape can also be applied to a capstan motor or the like.

以上説明したようにこの発明によれば、再生信
号より直接的に回転体の回転速度を制御すること
ができる。
As explained above, according to the present invention, the rotational speed of the rotating body can be directly controlled by the reproduction signal.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の速度制御回路の一例を示す図、
第2図はこの発明の一実施例を示すブロツク図、
第3図は第2図に示した実施例の各部の波形を示
す図である。 1……円盤、2……PU、3……位置検出器、
4……パルス発生器、5……演算部、6……位相
比較器、7……増巾器、8……モータ、10,1
1……第1及び第2のゼロクロス検出器、12,
13……第1及び第2のランプ発生器、14……
比較器、15……ピークホールド回路、16……
差動増巾器、17……基準電圧源。
FIG. 1 is a diagram showing an example of a conventional speed control circuit.
FIG. 2 is a block diagram showing one embodiment of this invention.
FIG. 3 is a diagram showing waveforms of various parts of the embodiment shown in FIG. 2. 1... Disc, 2... PU, 3... Position detector,
4... Pulse generator, 5... Arithmetic unit, 6... Phase comparator, 7... Amplifier, 8... Motor, 10, 1
1...first and second zero cross detectors, 12,
13...first and second lamp generators, 14...
Comparator, 15... Peak hold circuit, 16...
Differential amplifier, 17...Reference voltage source.

Claims (1)

【特許請求の範囲】 1 最長反転間隔(Tmax)がビツト周期(T0)
に対しTmax=n×T0(nは自然数)なる関係で
規制されたデジタル信号が記録された記録媒体よ
り再生される再生信号が入力され、再生信号の第
1および第2の極性変化点にて第1および第2の
リセツト信号を出力する第1および第2のゼロク
ロス検出器と、 上記第1および第2のリセツト信号によりリセ
ツトされ時間とともにその値が増加する第1およ
び第2のランプ信号を出力する第1および第2の
ランプ発生器と、 上記第1および第2のランプ信号の大きい方を
選択する比較器と、 この比較器の出力波形のピーク値を保持するピ
ークホールド回路と、 上記ピーク値と基準信号とを比較して記録媒体
を駆動する駆動系の制御信号を作成する手段とを
備え、 記録媒体に記録されたデジタル信号の記録密度
が変化した場合にも再生信号のビツト伝送速度が
一定となるべく記録媒体の速度を制御するよう構
成した事を特徴とする速度制御装置。
[Claims] 1. The longest inversion interval (Tmax) is the bit period (T 0 )
A reproduction signal reproduced from a recording medium on which a digital signal regulated according to the relationship Tmax=n×T 0 (n is a natural number) is input, and at the first and second polarity change points of the reproduction signal. first and second zero cross detectors that output first and second reset signals; and first and second ramp signals that are reset by the first and second reset signals and whose values increase over time. a comparator that selects the larger of the first and second ramp signals; a peak hold circuit that holds the peak value of the output waveform of the comparator; and a means for comparing the peak value with a reference signal to create a control signal for a drive system that drives the recording medium, so that even when the recording density of the digital signal recorded on the recording medium changes, the bits of the reproduced signal can be adjusted. A speed control device characterized in that it is configured to control the speed of a recording medium so that the transmission speed is constant.
JP56212982A 1981-12-25 1981-12-25 Speed controller Granted JPS58114356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56212982A JPS58114356A (en) 1981-12-25 1981-12-25 Speed controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56212982A JPS58114356A (en) 1981-12-25 1981-12-25 Speed controller

Publications (2)

Publication Number Publication Date
JPS58114356A JPS58114356A (en) 1983-07-07
JPH0357548B2 true JPH0357548B2 (en) 1991-09-02

Family

ID=16631501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56212982A Granted JPS58114356A (en) 1981-12-25 1981-12-25 Speed controller

Country Status (1)

Country Link
JP (1) JPS58114356A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223490A (en) * 1984-04-20 1985-11-07 Ricoh Co Ltd rotary drive device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5869484A (en) * 1981-10-16 1983-04-25 Sanyo Electric Co Ltd Control circuit for motor
JPS5883365A (en) * 1981-11-10 1983-05-19 Sony Corp Disk player

Also Published As

Publication number Publication date
JPS58114356A (en) 1983-07-07

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