JPH0358022U - - Google Patents

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Publication number
JPH0358022U
JPH0358022U JP11947189U JP11947189U JPH0358022U JP H0358022 U JPH0358022 U JP H0358022U JP 11947189 U JP11947189 U JP 11947189U JP 11947189 U JP11947189 U JP 11947189U JP H0358022 U JPH0358022 U JP H0358022U
Authority
JP
Japan
Prior art keywords
pair
circuit
input
signal
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11947189U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11947189U priority Critical patent/JPH0358022U/ja
Publication of JPH0358022U publication Critical patent/JPH0358022U/ja
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例であり、ミユーテイン
グ回路を示すブロツク図、第2図は動作を説明す
るタイミングチヤート図である。第3図は従来の
ミユーテイング回路を示す図である。 11……プリアンプ、14……メインアンプ、
17,18,19……第1の時定数回路、17,
20,21……第2の時定数回路、22……NP
Nトランジスタ、23……PNPトランジスタ、
24……信号ライン。
FIG. 1 shows an embodiment of the present invention, and is a block diagram showing a muting circuit, and FIG. 2 is a timing chart explaining the operation. FIG. 3 is a diagram showing a conventional muting circuit. 11... Preamplifier, 14... Main amplifier,
17, 18, 19...first time constant circuit, 17,
20, 21...second time constant circuit, 22...NP
N transistor, 23...PNP transistor,
24...Signal line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] NPN型とPNP型からなる一対のトランジス
タスイツチを増幅回路信号ラインとアース間に並
列接続すると共に、上記一対のトランジスタのベ
ース入力に電源オン・オフ信号を入力される微分
回路を設けたことを特徴とするミユーテイング回
路。
A pair of transistor switches consisting of an NPN type and a PNP type are connected in parallel between the amplifier circuit signal line and the ground, and a differentiating circuit is provided to input a power on/off signal to the base input of the pair of transistors. Muting circuit.
JP11947189U 1989-10-12 1989-10-12 Pending JPH0358022U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11947189U JPH0358022U (en) 1989-10-12 1989-10-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11947189U JPH0358022U (en) 1989-10-12 1989-10-12

Publications (1)

Publication Number Publication Date
JPH0358022U true JPH0358022U (en) 1991-06-05

Family

ID=31667597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11947189U Pending JPH0358022U (en) 1989-10-12 1989-10-12

Country Status (1)

Country Link
JP (1) JPH0358022U (en)

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