JPH0358216B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] At least a main processor, a control memory, and a slave control device are connected to an internal bus, and the main processor executes a control program stored in the control memory. In particular, in a data processing device that controls a slave control device, even if the main processor accesses the slave control device, when the slave control device is unable to process the access, the When a request is made to send/receive data sent/received by the slave control device through the external interface via the internal bus in the form of a cycle steal, the access request from the main processor is suspended, and the control memory is sent/received. This allows memory access by cycle stealing to be performed preferentially.

[Industrial application field]

The present invention relates to a line scanning mechanism (scanner) included in, for example, a communication control device (CCP),
In particular, the present invention relates to a memory access control method using cycle stealing from the slave controller to the control memory in a data processing device in which a control memory, a main processor, and a slave controller are connected via an internal bus.

As a form of recent data processing equipment, a main processor, a control memory, and a slave controller that processes a large amount of data from an external interface in real time are connected to an internal bus. There is a device that reads/writes a large amount of data processed in the above control memory in the form of a cycle steal.

For example, in a line scanning mechanism (scanner) in a communication control device (CCP), the internal bus of the device has a main processor, a control memory, and data exchange between multiple lines based on instructions from the main processor. Assemble the bit data into a character,
A slave control device is connected to which the character data stored in the control memory in the form of cycle steals or read out from the control memory in the form of cycle steals is decomposed into bit data and sent to the line, and the main processor By executing a control program stored in the control storage and accessing the slave control device, data exchange between the host computer and the line is controlled.

In this case, with the recent progress in online data processing and the increase in processing volume, the number of lines and speeds have increased, and the data read/write mechanism based on cycle stealing is becoming more and more difficult. High performance is increasingly required.

Another example of data processing that requires data to be exchanged with a storage device in a cycle-steal format by running on its own according to the instructions of the main processor is processing data from a large number of sensors. There are sensor systems that need to process time data, and robot systems that need to send a large amount of data processed by a host computer to a large number of control mechanisms in real time.

In either case, instructions from the host computer are received by the main processor, for example, by executing a control program in which control memory is stored.
The information is sent to the slave controller, and according to the instructions, the slave controller connects the external interface (e.g.
Data is exchanged with the line support unit in the communication control device, the sensor support unit in the sensor system, the robot control unit in the robot system, etc.), and the data is stored in the storage device of this data processing device in the form of a cycle steal. The place has its own characteristics.

Therefore, after data is transmitted and processed in real time from the upper external interface by access to the slave control device from the main processor, the cycle steal operation for transmitting and receiving data to and from the storage device is not hindered. Steel control method is required.

[Conventional technology]

The main processor, control memory, and slave control device are connected to one internal bus, and the slave control device runs on its own according to instructions from the main processor, allowing data to be sent from the external interface in real time. A line scanning mechanism (scanner) in a communication control unit (CCP) is an example of a data processing device that sends and receives data, performs specific processing, and then reads and writes the data to a storage device in the form of a cycle steal.
However, the conventional data processing method in the line scanning mechanism (scanner) will be explained below.

FIG. 3 is a diagram showing an example of the configuration of a conventional line scanning mechanism (scanner).

Data is exchanged in such a data processing device through the data path 7, which is roughly divided into the following three types. (1) A first path between the main processor (CSP) 1 and the control memory 3 for exchanging message data for each line by control program fetch or cycle steal.

(2) Main unit for initializing the slave control device (FES) 2, reading status such as error information in the slave control device (FES) 2, writing control information for controlling line scanning, etc. A second path between the processor (CSP) 1 and the slave controller (FES) 2.

(3) Assemble and disassemble the data to be sent and received in bit units between the line (LUT) and the LUT interface circuit 6 in character units, and send and receive the data to and from the control memory 3 in a cycle steal format. a third path between the slave controller (FES) 2 and the control store 3;

It is.

The cycle steal control unit 4 performs priority control of the above three paths. The cycle steal by the third path from the slave control device (FES) 2, which normally requires real-time processing, is set to have the highest priority.

The operation of the line scanning mechanism (scanner) described above is summarized below.

First, in the main processor (CSP) 1, a control program is fetched from the control memory 3, and a line scanning operation is performed by executing the program.

Specifically, the second path (data bus 7,
After initialization of the slave control device (FES) 2 is performed by the address buses 8a and 9), the line scanning cycle and the like are set, and the line scanning operation is started.

As a result, the data from each line (LUT) is
The data is once stored in the internal memory of the slave control device (FES) 2 in bit units, and at the point when data for, for example, two characters has been stored for each line, the slave control device (FES) 2 activates the cycle steal control unit. 4
Then, a cycle steal request and an address for the control memory 3 are sent to the control line and address bus 8b.

When the cycle steal control unit 4 recognizes the cycle steal request, it stores the character data in the cycle steal format in the area corresponding to the line in the control memory 3 with the highest priority.

In this way, when the character data stored in the area corresponding to each line of the control memory 3 becomes a predetermined message unit, for example, the character data stored in the area corresponding to each line of the control memory 3 is sent to the main processor (CSP) 1 from the slave control device (FES) 2.
The main processor (CSP) 1 reads the message from the control memory 3 in the form of a cycle steal, and sends it to the host computer (not shown) through the IOC bus controller 5. do.

A similar procedure is used to send data from the host computer to each line (LUT).

[Problem that the invention seeks to solve]

In such a conventional system, once processing related to the first pass or the second pass (for example, control program fetch, instruction execution, etc.) is started in the main processor (CSP) 1, Until the processing is completed, the slave control device (FES) 2
The cycle steal operation associated with the third pass could not be performed.

FIG. 4 is a time chart showing an example of the operation (for example, operation related to the first and second paths) in the main processor (CSP) 1. , an instruction fetch, a decoding operation of the instruction, and an access (data load/store) to the slave control unit (FES) 2 by the instruction are executed as one instruction execution cycle.

During this one instruction execution cycle, the data path 7 is busy.

However, in the slave control device (FES) 2, as shown in the time chart of FIG. (corresponding to the figure) and the processing in the slave control device (FES) 2 itself, that is, the execution timing of the cycle steal (SEND, RECV) cycle for the control memory 3 is fixed, so the instruction from the main processor (CSP) 1 Depending on the issuance timing of the instruction, the processing of the instruction may be executed by the next slave control device (FES).
It may be necessary to wait until the execution cycle '2.

This state is shown in , and when the execution of access via the second path from main processor (CSP) 1 is awaited, even though the normal cycle is the timing to be passed to cycle steal. Since the data path 7 is busy, there has been a problem in the slave control device (FES) 2 that even if a cycle steal request is generated for the control memory 3, it cannot be executed. This condition is.

FIG. 6 is a time chart showing the relationship between the access operation a for the second path from the main processor (CSP) 1 and the cycle steal operation b for the third path in the slave controller (FES) 2. This is a diagram in which main processor (CSP) 1 is
Depending on the timing of starting access to the path, the above-mentioned problem may occur if the cycle steal operation in the slave control device (FES) 2, which should be processed with the highest priority, is made to wait.

In this way, in the conventional method, even in a waiting state where the main processor (CSP) 1 cannot access the slave control device (FES) 2, the problem that occurs when the cycle steal operation in the slave control device (FES) 2 is made to wait is solved. It was hot.

In view of the above-mentioned drawbacks of the conventional art, the present invention provides a processor for cases where the main processor (CSP) 1 accesses the slave control device (FES) 2 but cannot perform the access, that is, the access is made to wait (see FIGS. 5 and 6). The purpose of the present invention is to provide a method of controlling the slave control device (FES) 2 so that the cycle steal operation can be processed preferentially.

[Means for solving problems]

FIG. 1 is a block diagram illustrating an embodiment of the present invention, in which even if a main processor (CSP) 1 accesses a slave control device (FES) 2, the timing of issuing the command is Therefore, if the slave control device (FES) 2 is forced to wait because it cannot execute the process for the access, and a cycle steal request with the highest priority occurs in the slave control device (FES) 2, , the cycle steal control unit 4 recognizes the request and sends an instruction execution inhibition signal 10 to the main processor (CSP) 1 to suspend execution of the instruction (for example, to inhibit sending of the instruction to the data bus 7). Configure it to send out.

[Effect]

That is, according to the present invention, at least a main processor, a control memory, and a slave control device are connected to the internal bus, and the main processor executes a control program stored in the control memory. Therefore, in a data processing device that controls a slave control device, even if the main processor accesses the slave control device, when the slave control device is unable to process the access, the slave control device When a request is made to send/receive data to/from the control memory via the internal bus in the form of a cycle steal, the device suspends the access request from the main processor and steals the cycle for the control memory. This has the effect that memory access by stealing can be performed preferentially, and real-time processing can be effectively executed in the slave control device.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 2 is a time chart showing one embodiment of the present invention, and the cycle steal operation in the slave control system (FES) when the present invention is implemented will be explained with reference to FIG.

First, the main processor (CSP) 1 accesses the slave control device (FES) 2 at the timing explained in FIG. Assume that the execution cycle ′ is kept waiting until the execution cycle ′.

This instruction execution waiting period is shown by a dotted line.
At this time, in the slave control device (FES) 2, data for, for example, two characters is accumulated in an area corresponding to a certain circuit on the internal memory (not shown).
When a cycle steal request and its address information are sent to the control memory 3 via the cycle steal control unit 4, the cycle steal control unit 4 recognizes that the instruction from the main processor (CSP) 1 is waiting. , the instruction execution inhibit signal 10 is sent to the main processor (CSP) 1.
is sent out, and the command sent from the main processor (CSP) 1 to the slave control unit (FES) 2 is suppressed on the data bus 7, thereby functioning to make the data bus 7 idle.

Therefore, the slave control device (FES) 2 can now perform a cycle steal operation on the control memory 3, and the data for the above two characters can be stored as follows.
It can be stored in an area of the control memory 3 corresponding to the above-mentioned line.

When the cycle steal operation is completed, the instruction execution inhibit signal 10 is released, so the main processor (CSP) 1 stops executing the suspended instruction.
This can be done in the next execution cycle' in the slave controller (FES) 2.

As described above, in the present invention, the main processor (CSP) 1 executes the control program stored in the control memory 3, so that the slave control device (FES) 2 autonomously scans the line. In this case, even if the main processor (CSP) 1 issues another access command to the slave controller (FES) 2, the slave controller (FES) 2 cannot process the access due to the timing conditions. When a cycle steal request is generated for the control memory 3 due to a line scanning operation in the slave controller (FES) 2, execution of the above instruction in the main processor (CSP) 1 is suppressed and the cycle steal operation is prioritized. It is unique in that it is possible to do so.

In this embodiment, the operation in the line scanning mechanism (scanner) in the communication control device (CCP) has been explained, but considering the gist of the present invention, the operation is not limited to the scanner operation, and the main processor By issuing a command, the self-running slave control device transfers the data processed in real time to the storage device of the data processing device.
For example, a data processing system exhibiting a processing form in which data is transmitted and received in the form of cycle stealing, and the execution of an instruction issued by a main processor is delayed depending on the operation timing of a slave control device, such as the aforementioned sensor system, It goes without saying that all of the above can be applied to robot systems, etc.

〔Effect of the invention〕

As described above in detail, in the cycle steal control method of the present invention, at least a main processor, a control memory, and a slave control device are connected to an internal bus, and the main processor stores data in the control memory. In a data processing device that controls a slave control device by executing a control program, even if the main processor accesses the slave control device, the slave control device does not respond to the access. When processing is not possible, when a request is made to send/receive data to/from the control memory via the internal bus in the form of a cycle steal, the slave controller receives an access request from the main processor. While the control memory is suspended, memory access by cycle stealing to the control memory can be performed preferentially, and there is an effect that real-time processing can be effectively executed in the slave control device.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart showing an embodiment of the present invention, and Fig. 3 is the configuration of a conventional line scanning mechanism (scanner). Figure 4 is a time chart showing an example of the operation in the main processor (CSP). Figure 5 is a time chart showing an example of the operation in the slave controller (FES). FIG. 6 is a time chart showing the relationship between the access operation of the main processor and the cycle steal operation of the slave control device. In the drawing, 1 is the main processor (CSP), 2
is the slave control unit (FES), 3 is the control memory, 4 is the cycle steal control unit, 5 is the IOC bus control unit, and 6 is the IOC bus control unit.
LUT interface circuit, 7 is data bus, 8
a, 8b, 9 are control and address buses, 10 is an instruction execution inhibit signal, ~, ' are each operation timing,
are shown respectively.

Claims (1)

[Scope of Claims] 1. A control memory 3 storing a control program, a main processor 1, an internal memory, and a plurality of slave control devices 2 provided with registers are connected by an internal bus 7, 1. A data processing device that exchanges information between a control memory 3 and a slave control device 2, wherein the internal memory and registers of the slave control device 2 are the control memory 3 seen from the main processor 1. A part of the address is assigned, and the main processor 1 uses the address to issue a load command or a store command to the slave control device 2, thereby updating the internal memory and registers. means for accessing and the slave control device 2
The main processor 1 issues a processing request for a load instruction or a store instruction to the slave control device 2, and the processing is carried out by the slave control device. If the slave controller 2 issues a cycle steal request to the control memory 3 while the processor 2 is unable to process the processor 2 and is forced to wait, the master processor 1 suspends execution of the above instruction. A cycle steal control method characterized by controlling so that cycle steal from a control device 2 to a control memory 3 can be executed preferentially.