JPH0358543A - Packet composing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a packet assembling device that temporarily stores data in a batza memory until the amount of data to be transmitted satisfies packetization conditions.

Conventional technology Figure 3 shows the configuration of a conventional packet assembling device.
A buffer memory 3 for temporarily storing the transmission data 401 to 407 inputted to the input terminal 1, and a data amount counter 4 for counting the amount of transmission data stored in this buffer memory and determining whether the packetization condition is satisfied. ,
According to the instruction signal 6 from the data amount counter 4, l packets of data 7 are read out from the buffer memory 3, and processing such as adding a header is performed to output packets 411 to 413.
The packet sending circuit 5 outputs the packet to the output terminal 2 as a packet.

FIG. 4 shows an operation timing diagram for explaining the operation of the packet assembling device shown in FIG.
407 is transmission data input in burst form to the packet assembly circuit; 411 to 413 are transmission data 401 to 407;
Output packets assembled into packets of constant length,
421 is a packet header indicating the destination of each packet and other additional information.

In FIG. 4', for the sake of simplicity, the transmission data 401 to 407 are manually input to the packet assembling circuit in a burst form, which is an integer multiple of the unit data amount indicated by the interval between the vertical lines in the figure. Furthermore, the amount of data transmitted by one packet is 5 units of data amount (
(transmission data corresponding to five intervals between vertical lines in the figure).

Now, assuming that the data lengths of the above-mentioned transmission data 401, 402, and 403 are 1 unit data amount, 2 unit data amount, and 3 unit data amount, respectively, 2 unit data amount of the transmission data 403 is accumulated in the buffer memory 3. At this point, the packetization conditions for the transmission data stored in the buffer memory are satisfied, and the packet is transmitted from the packet transmission circuit 5 as an output packet 411.

Furthermore, the final 1 unit data amount of the transmission data 403 is 3 of the transmission data 404 and the transmission data 405.
It is sent out as an output packet 412 together with data for a unit data amount. Similarly, the last 1 of the transmission data 405
Transmission data of unit data amount 4. 0 6 and transmission data 407 are sent out as output packet 413.

As described above, even in the conventional packet assembling apparatus shown in FIG. 3, transmission data inputted in bursts can be sent out as packets of a fixed length.

Problems to be Solved by the Invention However, in the conventional packet assembly device described above, since the packetization condition is that one packet's worth of transmission data is stored in the buffer memory, unsent data may remain in the buffer memory. If the remaining data remains, there is a problem that if the arrival interval of the next transmission data is long, the delay time until the unsent data accumulated in the buffer memory is sent out as a packet becomes large. Further, for this reason, when the burstiness of the transmitted data is large, there is a problem in that the variation in delay time becomes large.

The present invention solves these conventional problems,
It is an object of the present invention to provide an excellent packet assembling circuit capable of keeping the delay time until packet transmission within a certain period of time and reducing variations in delay time.

Means for Solving the Problems In order to achieve the above object, the present invention provides a timer circuit for measuring the time that data stays in the buffer memory, so that one packet of transmission data is stored in the buffer memory. In addition to being stored, the packetization condition is that the residence time of unsent data in the buffer memory reaches a certain time.

Therefore, according to the present invention, when the data retention time in the buffer memory reaches a certain period of time, the transmission data is packetized and transmitted, so that when the arrival interval of the transmission data to the packet assembling device is large, However, it has the effect of preventing the delay time until transmission data is sent out as a packet from becoming larger than a certain value.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 11 and 12 are the input and output terminals of the packet assembling device, 13 is a buffer memory for temporarily storing transmission data 201 to 207, and 14 is transmission data 201 to 207 stored in the buffer memory 13. 16 is a timer circuit that measures the residence time of the transmission data in the buffer memory 13; 17; are the respective instruction signals 20 from the data amount counter 14 and the timer circuit 16.
．． 21 is an input OR circuit, and 15 is a packet sending circuit that reads data 18 from the buffer memory in response to an instruction signal 23 output from the OR circuit 17 and sends it out as packets 211 to 214.

FIG. 2 is an operation timing chart for explaining the operation of the packet assembling apparatus according to the present invention shown in FIG. In FIG. 2, 201 to 207 are transmission data that are manually entered in bursts to the packet assembly circuit, 211 to 214 are output baguettes in which the transmission data 201 to 207 are assembled into packets of a certain length, and 221 is the destination of each packet. This is a packet header that indicates additional information such as the effective data length within the packet.

In addition, in FIG. 2, to simplify the explanation as in FIG. 4, the transmission data is sent to the packet assembling circuit in burst form as a set of integer multiples of the unit data amount indicated by the interval between the vertical lines in the diagram. It is assumed that the data is transmitted manually, and the amount of data transmitted by one packet is 5 units of data (transmission data for 5 intervals between vertical lines in the figure).

Next, the operation of the above embodiment will be explained. Writing transmission data to buffer memory 13, data amount counter 1
Counting the amount of data to be transmitted and instructing to send out packets by No. 4 are the same as in the conventional packet assembling circuit.

Now, assuming that the data lengths of the transmission data 201, 202, and 203 are respectively 1 unit data amount, 2 unit data amount, and 3 unit data amount, output packets 211 and 212 are output at the timing shown in FIG.

In other words, when two units of data of the data 203 are stored in the buffer memory 13, the packetization condition for the data stored in the buffer memory is satisfied, and the data is sent out from the packet sending circuit 15 as an output packet 211. . Furthermore, the final one unit data amount of the data 203 is sent out as an output packet 212 together with three data amounts of the transmission data 205.

Then, at the time when the transmission of the output packet 212 ends, the timer circuit 16 is reset by the packet transmission end signal 20 output from the packet transmission circuit 15 every time the transmission of the packet ends.

However, at this time, since the last unit data amount of the transmission data 205 remains unsent in the buffer memory 13, the timer circuit 16
In response to the data remaining amount signal 19 from the buffer memory 3, measurement of the data retention time in the buffer memory is started.

If the amount of data in the buffer memory does not reach one packet due to the arrival of new transmission data within a preset fixed time T after sending the output packet 212,
After time T, the timer circuit 16 outputs an instruction signal 21 instructing the packet sending circuit 15 to send the unsent packet.

In this case, data 1 read from the buffer memory 13
8 is less than the data amount for one packet, the packet sending circuit 15 adds dummy data 223 to the final one unit data amount of data 222 of the transmission data 205 and sends it out as an output packet 213.

In this way, according to the embodiment described above, even when the arrival interval of the transmission data to the packet assembling device is long, the residence time of the transmission data in the buffer memory can be kept within a certain period of time.

Effects of the Invention As described above, according to the present invention, a timer circuit is provided to measure the time that transmission data remains in the buffer memory, and in addition to a data amount counter that measures the amount of data in the buffer memory. Since the configuration is configured so that the transmission data is read out from the buffer memory and the packet is sent out also according to instructions from the timer circuit, even if the transmission data arrives at the packet assembling device at a long interval, the transmission data is not processed as a packet. It is possible to suppress an increase in the delay time until the signal is sent out, and it is possible to reduce variations in the delay time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a packet assembling device according to an embodiment of the present invention, FIG. 2 is an operation timing diagram for explaining the embodiment shown in FIG. 1, and FIG. 3 is a block diagram of a conventional packet assembling device. 4 are operation timing charts for explaining the operation of the packet assembling apparatus shown in FIG. 3. 13... Buffer memory, 14... Data amount counter, 15... Packet sending circuit, l6... Timer circuit, 201-207... Transmission data, 211-214
...Output packet.

Claims (1)

[Scope of Claims] A buffer memory that temporarily stores transmission data, a data amount counter that counts the amount of transmission data stored in the buffer memory, and a time period during which data remains in the buffer memory. a timer circuit; and a packet sending circuit that reads data from the buffer memory, generates a packet, and sends it when the data amount counter counts a predetermined amount of data or when the timer circuit measures a predetermined time. Equipped with packet assembly equipment.