JPH0358738U - - Google Patents

Description

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an electronic computer according to an embodiment of this invention, Fig. 2 is a flowchart showing details of operation according to an embodiment of this invention, and Figs. 3 and 4 are diagrams showing a conventional electronic computer. FIG. 2 is a configuration diagram showing two typical types. In Figure 1, 1 is the CPU, 2 is the ROM, 3 is the RAM, 4 is the bus, 5 is the installed program, 6 is the work area, 7 is the stack table area, 8 is the reprogram area, 9 is the scheduler program, 10 11 is a command program, 11 is a table load program, 12 is a subroutine program, 14 is stack table data, 18 is a reprogram, and 19 is a spare area. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Claims for Utility Model Registration] (1) In an electronic computer configured with a central processing unit that controls processing, a data read-only memory, and a data readable and writable memory,
The data read/write memory has a memory area that can store table data that defines the jump destination address and return destination of processing and a group of subroutine programs, and the read-only memory for the above data has a scheduler program and An electronic computer equipped with a memory area that can store table data load programs, command programs, and subroutine programs. (2) Utility model registration as described in claim (1), which is provided with a memory area that can store table data that defines a processing jump address and return destination as a triple system in a data readable/writable memory. electronic computer.