JPH0360066A - Input and output protecting device of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the prevention of the deterioration in performance of a semiconductor integrated circuit if a potential of an input terminal is changed over an L-level after an enough time has elapsed by inserting a first conductive type MOS transistor in which a gate is connected to an internal circuit side end of a first conductive type diffusion resistance layer between a trounding terminal and a second conductive type well where are first conductive type resistance layer to which an input terminal is connected is arranged. CONSTITUTION:An NMOS transistor 1 is formed in a P-type well 14a fixed to a ground level through a P-type diffusion layer 2a. One N-type diffusion layer 3a of the NMOS transistor is connected with a grounding level and another N-type diffusion layer 4 is connected with a P-type diffusion layer 7 in a P-type well 6 in which an N-type diffusion resistance layer 5 is formed. A gate 8 is connected to a drain of an input protecting transistor 9 and to an internal circuit. At this time, if an input level Vin is held at Vcc level, the input level fixes the gate 8 of the NMOS transistor 1 to a power source voltage level through the N-type diffusion resistance layer 5, so that an electric charge is not stored in the P-type well 6. Accordingly, even when Vin is changed over L-level in a moment, a delay caused by a time constant does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output protection device for a semiconductor integrated circuit.

[Conventional technology]

A conventional example will be described using an example in which the first conductivity type is N type.

Conventionally, this type of input/output protection device has an N-type buried layer 11 on a P-type Si substrate 10 fixed to the ground potential, as shown in the cross-sectional view of a semiconductor chip in FIG. 3 and the equivalent circuit diagram in FIG. , an N-type buried layer 11 and an N-type diffusion layer 12a, . . .
It has an N-type well 13 that is fixed to the power supply voltage via the N-type well 13.

Furthermore, an N-type diffused resistance layer 5 to which an input terminal is connected is provided in an electrically unfixed P-type well 6 that is separated from an adjacent element.
A parasitic pie-bored transistor 16 is made with the N type well 6 as the base and the N type diffused resistance layer 5 as the emitter.
n M O as a protection circuit after passing through type diffusion resistor N5
S transistor 9 was refined.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit input protection device described above, the P-type well for forming the N-type diffused resistance layer to which the input terminal is connected is not electrically fixed in order to obtain the strength of electrostatic withstand voltage. As a result, a parasitic bipolar transistor is formed in which the input terminal is the emitter, the N-type buried layer is the collector, and the P-type well is the open base.

If the level of the input terminal (hereinafter V11.) is left at the level (hereinafter Vl) I) which is sensed as the II H'' level as the power supply voltage, the junction bias between the collector and base of the parasitic bipolar transistor will decrease, and the P-type well The amount of charge accumulated in becomes very large.After that, ■ becomes “′′
At L° level, the charge accumulated in the P-type well is directed to the input terminal via the N-type diffused resistor with a time constant determined by the resistance value of the N-type diffused resistor, the amount of accumulated charge, and the hr of the parasitic bipolar transistor. This results in a discharge and a transition to the "L" level. This has the disadvantage that the performance of the semiconductor integrated circuit, for example, the speed decreases, is significantly degraded.

[Means to solve the problem]

The input/output protection device for a semiconductor integrated circuit of the present invention is surrounded by a first conductivity type well connected to a power supply potential terminal and a first conductivity type buried layer, and electrically isolated from a second conductivity type substrate. In an input/output protection device for a semiconductor integrated circuit having a first conductivity type diffused resistor connected to an external terminal formed in a second conductivity type well in a region, a gate terminal is connected to the first conductivity type diffused layer resistor. The MOS transistor has a drain terminal connected to the second conductivity type diffusion layer in the second conductivity type well, and a source terminal connected to the ground potential.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram.

The difference from the conventional example is that nMOS) transistor 1
is formed in a P-type well 14a fixed to the ground level via a P-type diffusion layer 2a, the N-type diffusion layer 3a of this nMOSMOS transistor is fixed to the ground level, and the other N-type diffusion layer 4 is fixed to the ground level. It is connected to a P-type diffusion layer 7 in a P-type well 6 in which a type diffusion resistance layer 5 is formed, and a gate 8 is connected to a drain of an input protection transistor 9 and an internal circuit.

Next, the operation of this embodiment will be explained.

For example, the input level ■ is V. Let's consider a state where it is held at C level. In this case, the input level is fixed to the power supply voltage level through the N-type diffused resistor N5 to the gate 8 of transistor 1, so transistor 1 is ON.
It functions to release the electric charge of the P-type well 6, in which the N-type diffused resistor N5 is provided, to the ground. Therefore, charges are not accumulated in the P-type well 6. Therefore, there is no delay at all due to the time constant even when the signal (■) is instantaneously changed to the L'' level.

In the above description, it is clear that the present invention can also be applied to devices in which the conductivity type is reversed and the polarity of the power source is changed.

〔Effect of the invention〕

As explained above, in the present invention, the gate is placed between the ground terminal and the second conductivity type well provided with the first conductivity type diffused resistance layer to which the input terminal is connected. By inserting a MO3) transistor of the first conductivity type connected to the internal circuit side of the well, charges will not be accumulated in the well of the second conductivity type even when the potential of the input terminal is fixed at the power supply voltage level. This has the effect that even if the potential of the input terminal is switched to the "LIT" level after a sufficient period of time, the semiconductor integrated circuit can be operated without losing its original performance.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a semiconductor chip showing an embodiment of the semiconductor input/output protection device of the present invention, Fig. 2 is an equivalent circuit diagram of this embodiment, and Fig. 3 is an input/output of a conventional semiconductor integrated surface circuit. A cross-sectional view of a semiconductor chip showing a protection device, FIG. 4 is an equivalent circuit diagram of a conventional example, 1...nMO3) transistor, 2a
~2e... N-type diffusion layer, 3, 4... N-type diffusion layer, 5
...N-type diffused resistance layer, 6...P-type well, 7...
P-type diffusion layer, 8...nMO3) transistor gate, 9
... Input protection transistor, 10... P type St substrate, 11... N type buried layer, 12a to 12d... N
Type diffusion layer, 13...N type well, 14a, 14b...
- P type well, 15... external terminal, 16... parasitic bipolar transistor, 17... N type epitaxial layer.

Claims (1)

[Claims] In a region surrounded by a first conductivity type well in which a first conductivity type diffusion layer connected to a power supply potential end and a first conductivity type buried layer are electrically isolated from a second conductivity type substrate. the second of
A first terminal connected to an external terminal formed in the conductivity type well.
In an input/output protection device for a semiconductor integrated circuit having a conductive type diffused resistor, a gate terminal is connected to a first conductive type diffused layer resistor connected to the external terminal, and a gate terminal is connected to a second conductive type well formed in the second conductive type well. An input/output protection device for a semiconductor integrated circuit characterized by inserting a MOS transistor having a drain terminal connected to a type diffusion layer and a source terminal connected to a ground potential.