JPH0360075A - Manufacture of vertical field effect transistor - Google Patents

Abstract

PURPOSE:To realize a short channel length and to accelerate an operation by severely controlling the channel length using molecular layer epitaxy when a channel region of a vertical field effect transistor is formed. CONSTITUTION:A P-type channel region 3 is formed in a state that a N<+> type drain region 2 is formed by an ion implantation or epitaxial technique on a P-type silicon substrate 1 by molecular layer epitaxy. In this case, since an autodoping and solid diffusion are suppressed to very small values, the channel length can be much shortened to several hundreds Angstrom or less. When the region 3 is formed, if pressure of B2H6 gas to be introduced at the start and end of formation is lower and pressure in vacuum is raised, an electric field intensity near adhering is weakened, and a transistor having small short-channel effect can be formed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a vertical field effect transistor.

[Summary of the invention]

In the present invention, when forming the channel region of a vertical field effect transistor, the channel length is strictly controlled by 1I11 using molecular layer epitaxial growth method, and by realizing an extremely short channel length, the channel region is increased in speed. By forming the region so that the impurity concentration is high at the center of the channel and low near the source and drain, the electric field can be weakened and the generation of hot carriers can be suppressed.

[Conventional technology]

In the prior art, when forming a vertical field effect transistor, p-type and n-type regions are formed using ion implantation or normal epitaxial techniques.

[Problem to be solved by the invention]

In the above conventional technology, in ion implantation,
Because impurities have a Gaussian distribution, and in normal epitaxial technology, autodoping and solid-phase diffusion of impurities have a large effect, so the channel region is formed to a thickness of several hundred λ or less with good controllability of the film thickness. There was a lesson that it was difficult to do so.

Means for Solving the Problems] In order to solve the above problems, the present invention uses a molecular layer eviaxial growth method to form a conductivity type opposite to that of the drain region on the drain provided on the surface of the semiconductor substrate. We decided to form a region with

[Effect]

According to the above means, autodoping and solid phase diffusion can be suppressed to a very low level compared to when normal epitaxial technology is used, so the channel length of a vertical field effect transistor can be extremely shortened to several hundred λ or less. It is possible to

〔Example〕

In the following, a detailed explanation of the invention will be given.

FIG. 1 is a process diagram of an embodiment of the present invention. Figure 1fa
1 indicates that an n'''' drain region 2 is formed on a P-type silicon substrate 1 by ion implantation or epitaxial technology.

In this state, a channel region 3 is formed using a molecular layer epitaxial growth method. When using the molecular layer epitaxial growth method, if gas is introduced at 825°C as shown in Figure 2, the pressure at the time of 5ilhc7z introduction will be 1.5
X 10-'T. rr+ 5 of the pressure at the time of introduction of B2H4
i11. Assuming that the ratio to cJ is 2XlO-', as shown in Figure 3, the fourth
As shown in the figure, a P-type film with a B concentration of IXIO"Cm-" is formed. Therefore, if gas is introduced for 500 cycles, a P-type channel region 3 with a thickness of 700 mm is formed as shown in FIG.

Here, when forming the channel region 3, by lowering the BtHh pressure at the beginning and end of the formation and increasing the pressure at the center, the electric field strength near the junction can be weakened and a transistor with a small short channel effect can be formed.

Next, as shown in FIG. 1 (C1), an n source region 4 is formed.

Next, as shown in FIG.
Form a hole that reaches . Next, gate oxide M5 is formed inside the hole by thermal oxidation or CVD as shown in FIG. 1 (el).

Furthermore, as shown in FIG. 1 (fl), polycrystalline silicon is deposited and then patterned to form a gate electrode 6.

〔Effect of the invention〕

According to the molecular layer epitaxial growth method, autodoping and solid phase diffusion can be suppressed to a much lower level than when using normal epitaxial techniques, so the film thickness of the channel region of a vertical field effect transistor can be reduced to several hundreds of amps. less than,
The formation can be controlled with precision by several people, and furthermore, the impurity concentration distribution in the channel region can be controlled.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view showing the process of an embodiment of the present invention, Fig. 2 is a time chart of an example of the gas introduction pressure during molecular layer epitaxial growth, and Fig. 3 is the ratio of the pressure at the time of introduction of B z II b to 5ilhCjz. FIG. 4 is a diagram showing the relationship between the growth film thickness per 1 cycle and
FIG. 3 is a diagram showing the relationship between the ratio of the pressure at the time of introduction of b to 5 iHzCJz and the B concentration in the film.・P-type silicon substrate ・N・Drain region ・Channel region ・N゛source region Gate oxide film ・Gate electrode

Claims (2)

[Claims] (1) A channel region with a strictly controlled channel length is created by forming a region with a conductivity type opposite to that of the drain region on the source or drain provided on the surface of the semiconductor substrate using a layer epitaxial growth method. A method for manufacturing a vertical field effect transistor, characterized by forming a vertical field effect transistor. (2) A method for manufacturing a vertical field effect transistor, characterized in that when forming the channel region, the impurity concentration is high in the center of the channel and the impurity concentration is low near the source and drain.