JPH0360226B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a high resolution solid state device for reproducing high definition images.

[Technical background of the invention and its problems]

Conventional television standard systems, such as the NTSC system, specify 512 vertical scanning lines, interlaced scanning with 2 feeds per frame, and a screen aspect ratio of 3:4. is configured to comply with this standard.

Currently, the number of pixels in, for example, an interline transfer type CCD (hereinafter referred to as IT-CCD) that conforms to this standard method is approximately 500 (vertical) x 400 (horizontal).

The imaging operation of such an IT-CCD will be briefly explained using FIG. In this IT-CCD, for example, a photodiode (hereinafter referred to as PD) is used.
2N×M photosensitive parts (for example, N=250, M=400)
P ₁₁ , P ₁₁ ′, P ₁₂ , P ₁₂ ′, …, P _1N , P _1N ′, P ₂₁ ,
P ₂₁ ′, P ₂₂ , P ₂₂ ′,…, P _2N , P _2N ′,…, P _M1 ,
P _M1 ′, P _M2 , P _M2 ′, …, P _MN , P _MN ′ (hereinafter Pi,
(represented by Pi') and vertical CCD registers _C1 , _C2 ,...
C _M are arranged horizontally alternating with each other. The signal charges in the vertical CCD registers are transferred stage by stage to the horizontal CCD register 1, which is a horizontal charge transfer unit, and are sequentially read out from the output unit 2 after being transferred within the horizontal CCD register 1 during the horizontal valid period. 4 shows the signal charges of the photosensitive parts Pi and Pi′ using the vertical CCD.
This is a field shift gate for reading data into registers C ₁ , C ₂ , . . . _CM .

Here, the number of vertical transfer stages in _the vertical _CCD registers _{C 1} , C ₂ , . In the normal television standard system, one frame consists of two fields, and interlace scanning is performed. Therefore, the IT-CCD also performs an imaging operation compatible with this, and divides the previous two fields into A and B fields, and in the A field, two photosensitive parts P ₁₁ , which are consecutively provided in the vertical direction, are used.
P ₁₁ ′, P ₁₂ , P ₁₂ ′, …, P _1N , P _1N ′, P ₂₁ , P ₂₁ ′,
P ₂₂ , P ₂₂ ′,…, P _2N , P _2N ′,…, P _M1 , P _M1 ′,
The signal charges accumulated in P _M2 , P _M2 ′, ..., P _MN , P _MN ′ are read out together, and in the B field, the signal charges are
Two consecutive photosensitive areas P ₁₁ ′, P ₁₂ , P ₁₂ ′, P ₁₃ , ..., P ₂₁ spatially have a phase difference of 180 degrees in the vertical direction with respect to the two photosensitive areas read out in the field. ′、
P ₂₂ , P ₂₂ ′, P ₂₃ ,…, P _M1 ′, P _M2 , P _M2 ′, P _M3 ,…
The accumulated signal charges are read out together. Such signal charge readout mode is called field accumulation mode. In this case, the spatial phases of the signals read out in fields A and B differ by 180 degrees in the vertical direction, so that 2N×M (= 500
*400 sample points are obtained.

These sample points are shown in FIG. The A field is represented by a black circle, and the B field is represented by a white circle. This sample point is set at the midpoint between two consecutive pixels in the vertical direction. The A and B field sample points are arranged in a square grid as seen in the figure.

With this conventional IT-CCD, the number of sample points per field time is 250 vertically, and
There are 400 sample points, and in 2 field periods due to interlacing, the vertical is doubled to 500 sample points,
The total sample points are 200K. Looking at these images, the vertical direction is the same sample point as the image pickup tube, so there is no problem, but the horizontal direction is quite poor.
400 is insufficient for the number of pixels in the horizontal direction,
There are demands to double the number to 580 or even 800. However, incorporating twice the number of pixels into the same silicon chip requires extremely fine integrated circuit fabrication technology, and it will take many years to put it into practical use.

As a method for pseudo-increasing the number of pixels without directly increasing the number of pixels, a method is used for MOS image sensors that uses a so-called checkerboard arrangement (also called an interpolation arrangement) of pixels and adopts two-row simultaneous readout interlacing (References : Journal of the Television Society Vol. 37 No. 10 812
~818 pages). In MOS type elements, the readout line is Al
Vertical and horizontal wiring is easy, and two rows (two pixels in the vertical direction) are read out at the same time, and the obtained signals are output separately from two signal lines, making it easy to delay half a pixel shift externally. By adjusting the line by half a bit, the time signal can be made to correspond to the original pixel position.

On the other hand, in IT-CCD, the checkered pixel arrangement is
It is necessary to meander the vertical transfer CCD, making the configuration complicated. Furthermore, as described above, two pixels in the vertical direction are read out simultaneously, but since the number of CCD stages is half the number of pixels, they cannot be held separately and must be combined at the beginning of transfer.

In this way, increasing the resolution of IT-CCDs inevitably requires a more complex structure, and simply increasing the number of pixels is being pursued as a solution.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a solid-state imaging device that reproduces high-definition images while taking advantage of the characteristics of IT-CCD, which is excellent in terms of noise and sensitivity.

[Summary of the invention]

In the solid-state imaging device according to the present invention, the vertical charge transfer section has a one-stage structure per pixel in which one charge transfer stage is formed for each pixel in the vertical direction;
A first operation mode in which signal charges for two vertically consecutive pixels of the vertical charge transfer section are added to the horizontal charge transfer section at the same position, and a first operation mode in which signal charges for two pixels in different rows and columns of the vertical charge transfer section are added. It is characterized by having a second operation mode in which signal charges are added at the same position. As the vertical charge transfer section as described above, for example, the present inventors have proposed the
The one published in Publication No. 161473 (filing date S57.2.19) may be used.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a high-resolution solid-state imaging device with twice the resolution in the horizontal direction using conventional integrated circuit technology without physically increasing the number of pixels in the horizontal direction.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a schematic configuration diagram of a solid-state imaging device according to an embodiment of the present invention. M rows of photosensitive sections P ₁ , P ₂ , ..., P _M formed by photodiodes PD and M rows of vertical CCD registers C ₁ , C ₂ , ..., _CM are arranged alternately as shown in the figure. Each column of the part is P ₁₁ ,
P ₁₁ ′, P ₁₂ , P ₁₂ ′, P ₁₃ ,…, P _1N , P _1N ′, P ₂₁ ,
P ₂₁ ′, P ₂₂ , P ₂₂ ′, P ₂₃ ,…, P _2N , P _2N ′,…, P _M1 ,
Like P _M1 ′, P _M2 , P _M2 ′, P _M3 ,…, P _MN , P _MN ′
2N PDs are arranged, and each vertical CCD register has C ₁₁ , C ₁₁ ′,
C ₁₂ , C ₁₂ ′, C ₁₃ ,…, C _1N , C _1N ′, C ₂₁ , C ₂₁ ′,
C ₂₂ , C ₂₂ ′, C ₂₃ ,…, C _2N , C _2N ′,…, C _M1 ,
Like C _M1 ′, C _M2 , C _M2 ′, C _M3 ,…, C _MN , C _MN ′
It has 2N transfer stages. That is, perpendicular to the photosensitive area.
CCD registers are arranged alternately and vertical CCD
The number of register transfer stages and the number of vertical PDs are the same. Therefore, if N is set to 250 for example, the vertical direction
The number of PDs and the number of transfer stages of vertical CCD registers are both 500.

Figure 4 shows the configuration of the vertical CCD register. The cross section is taken in the vertical direction of the vertical CCD register.
An N ⁺ layer 11, which is a buried channel, is provided on a P-type silicon substrate 10, and a first gate oxide film 12 is formed on this N ⁺ layer 11. Then, a first layer transfer electrode 15 is formed on this gate oxide film 12.
(15-1, 15-2, 15-3,...) are formed, and a second gate oxide film 13 is interposed thereon.
Layer transfer electrodes 16 (16-1, 16-2,...)
is formed with an overlapping portion A _O with the first layer transfer electrode 15. And on top of that there is a third
A third layer transfer electrode 17 is formed continuously in the vertical direction with the gate oxide film 14 interposed therebetween. Here, the third layer transfer electrode 17 is arranged to face the substrate at a gap where the first layer transfer electrode 15 and the second layer transfer electrode 16 do not overlap.

By applying independent three-phase clock pulse voltages to the first layer transfer electrode 15, the second layer transfer electrode 16, and the third layer electrode 17,
Vertical charge transfer is performed using three consecutive electrodes, for example, the range A _P in the figure, as one transfer unit.

The imaging operation using the configurations shown in FIGS. 3 and 4 will be described. First, the signal charges accumulated in all the photosensitive parts in the A field are simultaneously transferred to the vertical CCD register via the field shift gate 4. As described above, since the vertical CCD register has one stage per pixel, the signal charge of each pixel is individually held in each stage of the adjacent vertical CCD register. These signal charges are transferred step by step in the vertical CCD register downward in FIG. In a normal CCD, charges that are transferred one stage at a time and enter the horizontal CCD register 5 are transferred at high speed in the horizontal direction and sequentially read out from the output section 2.

On the other hand, in the solid-state imaging device of this embodiment, one row of charges entered into the horizontal CCD register 5 by one stage of vertical transfer is held as is, and one row of charges is added to the horizontal CCD register 5 by one more stage of vertical transfer. Horizontal transfer is performed after the charge is applied. By repeating this operation, two vertically consecutive
P ₁₁ , P ₁₁ ′, P ₁₂ , P ₁₂ ′,…P _1N , P _1N ′,…, P ₂₁ ,
P ₂₁ ′, P ₂₂ , P ₂₂ ′,…, P _2N , P _2N ′,…, P _M1 ,
The signal charges accumulated in P _M1 ′, P _M2 , P _M2 ′, . . . , P _MN , P _MN ′ are added and read out. this is horizontal
This is the first mode of operation in the CCD register.

Next, in the B field, the signal charges accumulated in all the photosensitive parts are simultaneously transferred to the vertical CCD register via the field shift gate 4. These signal charges are transferred vertically one stage at a time and sent to the horizontal CCD shift register 5.
Unlike the field, when the charge from _P22 enters the horizontal CCD register 5, it is not held as it is;
Send forward by one register stage (one column). Hereinafter, this will be referred to as 1-column forwarding. When one column is forwarded, the vertical CCD register is transferred one stage again, and another row of charges is sent to the horizontal CCD register 5. This charge comes from the photosensitive area with the dash, for example P ₁₁ '. After this, horizontal transfer is performed and the signal is read out. When this operation is repeated, the signal of the B field becomes the sum of the signal charges accumulated in the two photosensitive sections P ₁₁ ', P ₂₂ , P ₁₃ ', P _{24 .} . . in the diagonal direction. This is the second mode of operation with the horizontal CCD register.

FIG. 5 shows sample points obtained by combining these A and B fields. The black circle indicates the A field, which is the same as in FIG. 2, but the white circle B field is shifted by half in the horizontal direction, resulting in an orthorhombic lattice arrangement.

As one of the present inventors and other authors analyzed and showed, the horizontal resolution is generally improved in the orthorhombic lattice arrangement (Reference: Journal of the Television Society, Vol. 37, No. 10, pp. 819-825). . Since the orthorhombic lattice arrangement is a so-called checkerboard arrangement and an interpolation arrangement, the solid-state imaging device of this embodiment is based on IT-CCD, but
This means that the checkered arrangement of CCDs, which was previously thought to be difficult, has been achieved in terms of sampling. Note that since the sampling point of the B field is shifted by half a pixel in the horizontal direction, it is necessary to match the sampling point at a position delayed by half a pixel on the time axis of the horizontal signal. This adjustment is horizontal
This can be achieved as a half-bit delay by shifting the phase of the clock pulse to the CCD register by 180 degrees.

Of the operations explained in the above examples, especially horizontal
The first and second operation modes corresponding to the A and B fields in the CCD register will be explained in more detail. FIG. 6 is a diagram showing a part of FIG. 3 and the state of signal charge transfer, FIG. 7 is a timing diagram in the A field, and FIG. 8 is a timing diagram in the B field. As shown in FIG. 6, the configuration of this embodiment is that the vertical CCD register C ₁ has three phases of transfer electrodes ΦV ₁ , ΦV ₂ , ΦV ₃ , and the horizontal CCD register 5 has transfer electrodes of ΦH ₁ , ΦH _{2 .} , ΦH ₃ and ΦH ₄ . Then, the signal charge accumulated in the photosensitive area _P1 is transferred vertically by the field shift gate.
The electrode transferred to CCD register _C1 is assumed to be _ΦV2 .
The operation of transferring and outputting the signal charges will be explained below.

The timing diagram in field A in FIG. 7 shows the electrodes ΦV 1 , ΦV 2 , ΦV ₃ of the vertical CCD register and _the electrodes _{ΦH 1} , ΦH ₂ , ΦH _{3 , of the horizontal CCD register in synchronization with the horizontal blanking pulse HBL} .
The pulse applied to ΦH ₄ is shown. In other words, in the A field, 2 times during the horizontal blanking period.
Perform line shifts. This line shift operation is made possible by applying three-phase timing pulses to ΦV ₁ , ΦV ₂ , and ΦV ₃ as shown in FIG.
Since the two line shift operations are the same, the first line shift operation will be explained. Kotokino
Vertical CCD register at each time point from t ₁ to t ₇
The surface potential formed under each electrode ΦV ₁ , ΦV ₂ , ΦV ₃ of C ₁ and the signal charge Q stored in this potential
The situation is shown in Figure 6. Sequentially like this
By changing the pulse timing from t ₁ , t ₂ , . . . , t ₇ , the signal charge is transferred as shown by arrow P. This operation is similarly performed in the second line shift operation. During these two line shifts, ΦH ₁ and ΦH ₂ of the electrodes of the horizontal CCD register 5 are kept at high level, and ΦH ₃ and ΦH ₄ are kept at low level. As a result, ΦH ₁ of horizontal CCD register 5,
Two rows worth of signal charges are added under ΦH ₂ . This added signal charge is then read out to the output section by driving the horizontal CCD register 5.

Next, in the B field, a timing pulse as shown in FIG. 8 is applied to each electrode. In the B field, unlike the A field, the signal charge on the photosensitive area where no dots are formed in Fig. 3, for example P ₂₂ , is horizontal.
When it enters the CCD register 5, it is not held as is, but transferred to the output side for one stage. This operation is performed by horizontal CCD register transfer electrodes ΦH ₁ ,
This is possible by applying a pulse to ΦH ₂ , ΦH ₃ , and ΦH ₄ to transfer the amount equivalent to one stage during the intermediate period between the two line shift operations described above. i.e. vertical CCD
Perform the first line shift operation in the register,
Next, one stage is transferred to the output side using the horizontal CCD register. Then, a second line shift operation is performed using the vertical CCD register. This makes it possible, for example, to add the signal charges of the photosensitive portions P ₂₂ and P ₁₁ ' in FIG. Thereafter, when the added signal charges are read out by driving the horizontal CCD register 5, they are read out with a delay corresponding to 1/2 pixel. Here, the signal charge transfer in the line shift operation is the same as the operation described in FIG. 6.

Note that a 2-phase, 3-phase, or 4-phase CCD can be used as the horizontal CCD shift register. It is sufficient that each column corresponds to one horizontal CCD. Also, this horizontal
The gate mechanism for transferring charge from the vertical CCD register to the CCD shift register is
A part of the electrode, for example, the third electrode of the final stage CCD, may also be used, or a shift gate may be provided separately.

Further, in the B field, although the combination of different pixels in one column and diagonal pixels on the lower right in different rows in FIG. 3 was explained, a combination of diagonal pixels on the upper right, for example, P ₁₂ and P ₂₁ ' may also be used. However, in this case, when the electrode from the photosensitive section without a dash, for example _P12 , is fed into the horizontal CCD shift register, it is sent backward one step. Hereinafter, this will be referred to as one-column reverse feed. Therefore, it is necessary to read out the signal by horizontal transfer after adding a charge from a photosensitive part with a dash, for example, P ₂₁ '. In this case, since the horizontal CCD shift register needs to be sent backwards, a CCD whose transfer direction is predetermined (for example, a two-phase CCD) cannot be used, but a three-phase or four-phase CCD is used.

Note that since the present invention performs addition of pixels in a diagonal direction, an odd combination of pixels may appear at the edge of the effective screen. For this reason, dummy pixels or signal processing are required.

In the above embodiment, the conventional field accumulation mode in which two pixels are added in the vertical direction is set to field A or B, and the field accumulation mode in which two pixels in the diagonal direction are added is set to field B or A.
This is an example of a high-resolution solid-state imaging device in which sampling points of a 2-field, 1-frame system are arranged in a checkered pattern for each combination of fields. In this method, the number of sampling points is 2N×M (=500×400), which is the same as in the conventional IT-CCD, and the arrangement is changed, so the apparent horizontal resolution increases.

The solid-state imaging device of the present invention is characterized in that it can achieve high resolution by reliably doubling the number of sampling points. In other words, the number of sampling points can be doubled by capturing one frame of four fields using each field described in the above embodiment. That is, as shown in FIG. 9, in the A field, a sampling point marked with a black circle is formed by adding two vertical pixels in the same column. In the next B field, the combination is changed downward by one pixel in the vertical direction in interlacing, and sampling points marked with white circles are formed by adding diagonal pixels downward to the right. next field
In the case of field A', the combination is returned upward by one pixel in the vertical direction by interlacing, and a sampling point of a black triangle is formed by adding diagonal pixels downward to the right. Furthermore, when the next field is designated as field B', the combination is again changed downward by one pixel in the vertical direction by interlacing, and a white triangle sampling point is formed by adding two vertical pixels. Field A and field B' are horizontal CCD shift registers that add signal charges of two vertical pixels in the same column. In the B field, the signal charges that have previously entered the horizontal CCD shift register are sent backwards by one pixel, and then added to the signal charges of the pixels in the diagonal direction upward to the right in the next column. In field A', after one pixel is sequentially shifted in the horizontal CCD shift register, the signal is added to the pixel in the diagonal direction downward to the left in the next column. As a result of these operations, the sampling points are arranged in a square lattice as shown in the figure and are surely doubled, resulting in a high-definition, high-resolution solid-state imaging device. Note that the sampling order is not limited to A→B→A′→B′ but also A→
B'→A'→B is also acceptable. In addition, without being limited to the NTSC format, when capturing still images such as facsimile,
The above sampling order is A→A'→B→B',
A→A′→B′→B, A→B′→B→A′ or A→B→
B′→A′ is also fine. In either case, the point of increasing the number of sampling points is significant.

Addition of two vertical pixels in the same column is performed by stopping the movement of the horizontal CCD shift register, and addition of two diagonal pixels (two pixels in different rows) in adjacent columns is performed by adding one pixel worth into the horizontal CCD shift register. A feature of the solid-state imaging device of the present invention is that the signal charges of the remaining pixels (pixels located far away from the horizontal CCD) are sent and added after being forwarded by one column or backward by one column. In addition, 1 pixel and 1 level vertical
If we describe the CCD as a main component, it is a field created by the addition of two vertically continuous signal charges in the same column.
This results in the addition of signal charges in two stages arranged diagonally in different columns.

In the above-mentioned embodiment, a PD is used as the photosensitive part, and photoelectric conversion and signal charge accumulation are performed at the same position.
Although the present invention has been described using an IT-CCD, the present invention is not limited to this, and high resolution can be achieved using a solid-state imaging device based on an IT-CCD. The so-called 2 types of IT-CCD-based systems that have recently been attracting attention are
It is a hierarchical solid-state image sensor. Another embodiment of the present invention using this element will be described with reference to the drawings.

FIG. 10 is a sectional view of a solid-state imaging device according to another embodiment of the present invention. For example, an epitaxial P layer 22 is formed on a P ⁺ Si substrate 21, and the n ⁺ part 23 of the vertical transfer CCD and the photo-layer of the conventional IT-CCD are formed on this layer.
N ⁺ section 24 of storage diode similar to diode section
There is. As described above, the vertical transfer CCD constitutes a one-stage CCD with one pixel by the three-layer polysilicon electrode 25. A first Al electrode 26 is drawn out from the storage diode 24, and a second Al electrode 27 is further placed on top of it.
form. A polyimide layer 28 is used for separation between pixels and for smoothing the surface. An a-Si film 29 serving as a photoelectric conversion layer is formed on top of these, and an upper transparent electrode 30 is further formed. The lower part of the element becomes a solid-state scanning section 31, and the upper part becomes a photoelectric conversion section 32.
Note that the a-Si film of the photoelectric conversion section may have not only one layer but also two or three layers depending on the purpose, but this is not essential to the present invention and will therefore be omitted.

The solid-state imaging device shown in FIG. 10 is provided with a horizontal CCD shift register similar to the embodiment described above. The effective photosensitive area of the pixel is defined by the second Al electrode 27.

FIG. 11 shows a part of the pixel configuration when FIG. 10 is viewed from above. ,,... indicate the vertical CCD registers, the large rectangles 1a, 1a',..., 5b, 5b' indicate the pixels defined by the second Al electrode 27 in FIG. 10, and the small rectangles indicate the pixels defined by the second Al electrode 27 in FIG. Represents the connection with the storage diode. The signal charges photoelectrically converted by the a-Si film 29 are accumulated in the storage diode 24 through the second and first Al electrodes, and then transferred to the vertical CCD in the same way as a normal IT-CCD. Figure 11 shows the case where the pixels are arranged in a square lattice, and although the vertical structure is different, the effective planar structure is the same as in Figure 3, so there is a vertical CCD and a horizontal CCD with one pixel and one stage configuration. By adding the registers, the sampling points shown in FIG. 5 or 9 can be formed and high resolution can be achieved.

In this case, the A field at the sampling point in FIG.
The pixel and B field are the addition of two diagonal pixels 1a' and 2b. In FIG. 9, sampling points of a B field made up of two vertical pixels 1a' and 1b and an A' field made up of two diagonal pixels 1a' and 2a are added to these.

The present invention can also be applied to a two-story solid-state image sensor, but the pixel arrangement itself can be arranged in a checkered pattern. That is, as shown in FIG.
If the drawing direction of the second Al electrode shown in the figure is set in the opposite direction for each row, the pixel arrangement becomes checkered. In conventional monolithic CCDs, the structure of pixels in a checkered pattern is extremely complicated, but in a two-story solid-state image sensor based on IT-CCD, a checkered pattern can be easily formed. In Fig. 12, signal charges 1a to 1b' are vertical CCD
Transferred to the register, 2a to 2b' are also vertical
Transferred to CCD register. With this element, A field is 1a, 1a', 1b, 1b', 2a, 2
The signal charges are read out together like a', 2b, 2b', and in the B field, 1a', 1b, 1b', 1
When signal charges are read out at points c, 2a', 3b, 2b', and 3c, they become sampling points in the coarse square lattice arrangement shown in FIG. 2, which is the same as in a normal IT-CCD. (The lines c and c' are omitted in the figure.) In this embodiment, in the A field, 1a, 1a', 1b, 1b', 2a, 2a' and 2
The vertical CCD adds the signal charges in the same column like b, 2b', and the B field adds the signal charges 1a', 2b, 1b',
The signal charges of pixels such as 2c, 2a', 3b, 2b', and 3c whose vertical CCDs are in different columns to be transferred may be added. In the B field, for example, the signal charge 2b enters the horizontal CCD shift register and is sent forward one stage in the horizontal direction, where the signal charge 1a' is sent and added by vertical transfer. This operation results in the same orthorhombic lattice sampling points as in FIG. 5, improving the horizontal resolution.

Furthermore, if it is acceptable to form one frame with four fields, fields A' and B' are added to the fields A and B to form sampling points forming a square lattice as shown in FIG. 14. In other words, following the A field marked with a black circle and the B field marked with a white circle, 2a, 1a', 2b, 1b', 3a, 2a' and 3b,
2b' black triangle A' field further 1a', 1
Add the B' fields marked with white triangles b, 1b', 1c, 2a', 2b, 2b', and 2c. In the A' field, the pixels to be added have their signals transferred to the vertical CCD in another column, so the pixels with dashes, for example 1
The a' signal charge is sent backward by one stage in a horizontal CCD shift register, and then the signal charge of a pixel without a dash, for example 2a, is sent and added. In the B field, since each pixel is transferred to the vertical CCD in the same column, it is sufficient to perform addition for two vertical pixels in the horizontal CCD shift register section. When the sampling points shown in FIG. 14 are formed, the resolution in the horizontal direction is doubled, and a high-definition solid-state imaging device can be provided.

As explained above, the conventional IT-CCD's two-pixel, one-stage vertical CCD is replaced with a one-pixel, one-stage CCD, and the signal charges of two vertical pixels that have entered the vertical CCDs in the same column can be added together, and the signal charges can be added to the vertical CCDs in different columns. A high-resolution solid-state imaging device can be obtained by adding the signal charges of two diagonal pixels whose input rows are different after the horizontal shift register is forwarded or reversed by one column.

In the above embodiment, when focusing only on the photosensitive portion, all pixels are added in diagonal directions shifted by half a pixel horizontally. In terms of diagonal direction, horizontally 1.5
It is also possible to add diagonally shifted pixels. For example, in FIG. 12, the sampling points 2a' and 3b are the same as the sampling points 3a' and 2b,
The signal charge of 2b is converted to 1 by the horizontal CCD shift register.
Just move the column backwards and then add from 3a'. Further, 2a' and 3b are the same as 1a and 4b in the diagonal direction, which are shifted by 2.5 pixels in the horizontal direction, and the signal charge of 1b is sent backward three columns and then added to the signal of 4b'.
Addition in diagonal directions away from these pixels is not necessary in monochrome devices because it reduces resolution, but in color devices, the filters of the same color may be placed far apart, so it is necessary to increase the sampling points to increase resolution. effective.

In addition, in the checkered arrangement pixels in Fig. 12, the vertical CCDs that transfer the signal charges of 1a, ..., 5a without a dot and 1b, ..., 5b are located on the left side of each pixel area, 1a with a dot. ′，…，
A two-story structure with 5a', 1b', ..., 5b' on the right side is also possible. In this case, since the addition of 1a and 1a' in the A field is between vertical CDDs in different columns, the 1a' signal charge is sequentially sent one column by the horizontal CCD shift register and then added to the signal charge of 1a. Also, since 1a' and 2b of the B field are vertical CCDs in the same column, the signal charge of 2b is held in a horizontal CD shift register, and the signal charge of 1a' is added thereto. 2a and 1a' of A' field are vertical in the same row
Since the CCD and B' fields 1a' and 1b are vertical CCDs in different columns, the above-mentioned addition is performed for each using a horizontal CCD shift register.

In the present invention, electrons are used as an example of the signal charge, but the present invention can also be used in a solid-state imaging device that uses holes as the signal charge.

Further, the signal charges in the present invention are not limited to those generated by light, but may be generated by accelerated electrons, X-rays, etc., for example.

In the present invention, an example of increasing the resolution in the horizontal direction has been described, but the present invention can also be applied to increasing the resolution in the vertical direction in the same way.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional IT-CCD, FIG. 2 is a diagram showing spatial sampling points by the IT-CCD in FIG. 1, and FIG. 3 is a diagram showing an embodiment of the solid-state imaging device of the present invention. 4 is a cross-sectional view showing the configuration of the vertical transfer CCD register in FIG. 3; FIG. 5 is a diagram showing spatial sampling points by the solid-state imaging device of the present invention in FIG. 3; FIGS. 6 to 8 The figure is a diagram for explaining the specific operation for obtaining such a sampling point, FIG. 9 is a diagram showing another spatial sampling point by the above-mentioned solid-state imaging device, and FIG. 10 is a diagram showing the solid-state imaging device of the present invention. 11 is a diagram illustrating the pixel configuration of FIG. 10, FIG. 12 is a diagram illustrating another pixel configuration of FIG. 10, and FIGS. The figure is a diagram showing spatial sampling points according to the pixel configuration of FIG. 12. P ₁ , P ₂ ,..., P _M ...photosensitive part, C ₁ , C ₂ ,..., C _M
...Vertical CCD register (vertical charge transfer section), 2...
...Output section, 4...Field shift gate, 5...
...Horizontal CCD shift register (horizontal charge transfer section),
10...P-type silicon substrate, 11...n ⁺ layer, 1
2...First gate oxide film, 13...Second gate oxide film, 14...Third gate oxide film, 15 (15-
1,...15-i,...)...first layer transfer electrode,
16 (16-1,...,16-i...)...Second layer transfer electrode, 17...Third layer transfer electrode, A _P
...1 pixel area, A _O ...overlapping part, 21...P ⁺
Silicon substrate, 22...P layer, 23, 24...
n ⁺ part, 25...3-layer polysilicon electrode, 26...
... 1st Al electrode, 27 ... 2nd Al electrode, 28 ... polyimide layer, 29 ... a-Si film (photoelectric conversion film),
30... Upper transparent electrode, 31... Solid scanning section, 3
2...Photoelectric conversion section, 1a, 2a,..., 5a,...1
b', 2b',..., 5b'...pixel,,,...,...
...1 pixel 1 stage vertical CCD register.

Claims (1)

[Claims] 1. A signal charge storage section constituting a two-dimensionally arranged pixel that accumulates signal charges generated by irradiation of light, electrons, X-rays, etc. on a semiconductor substrate, and a signal charge storage section of this signal charge storage section. A solid state comprising: a vertical charge transfer section arranged along a vertical array to read out the signal charges; and a horizontal charge transfer section that receives one horizontal column of signal charges transferred from the vertical charge transfer section and sends the signal charges to an output section. In the imaging device, the vertical charge transfer section has a one-stage configuration for each pixel in which one charge transfer stage is formed for each pixel arranged in the vertical direction, and the horizontal charge transfer section has a structure in which one charge transfer stage is formed for each pixel arranged in the vertical direction. High-resolution solid-state imaging characterized by having a first operation mode in which signal charges for two pixels are added together and a second operation mode in which signal charges for two pixels in different rows of adjacent horizontal columns are added. Device. 2. The high-resolution solid-state imaging device according to claim 1, wherein the vertical charge transfer section with a one-pixel, one-stage configuration is composed of three layers of transfer electrodes. 3. The second operation mode of the horizontal charge transfer section is:
The patent claim is characterized in that the signal charge that first enters the horizontal charge transfer section among the signal charges for two pixels to be added is sent forward or backward so that the signal charges of other columns are received in an overlapping manner. A high-resolution solid-state imaging device according to scope 1. 4. The high-resolution solid-state imaging device according to claim 1, wherein the horizontal charge transfer section is capable of forward and reverse transfer by three-phase or four-phase driving. 5. The high-resolution solid-state imaging device according to claim 1, wherein an imaging operation of 2 fields/1 frame is performed with the A field in the first operation mode and the B field in the second operation mode. . 6. The high-resolution solid-state imaging device according to claim 1, wherein the photoelectric conversion section has a two-story structure superimposed on the signal charge storage section separately from the signal charge storage section.