JPH036120A - Simultaneous conduction prevention circuit for power transistor circuit - Google Patents

Abstract

PURPOSE:To prevent destruction due to an overcurrent from occurring by connecting a logic circuit which interrupts a state where a power transistor for charge control and a power transistor for discharge control are turned on simultaneously to a switching control circuit. CONSTITUTION:When a pulse shape signal S1 is applied on a control signal input terminal 8 from the outside as a control signal to perform the charge/ discharge control of a piezoelectric element 1, the rise and fall timing of the output signal S2 of a NOT gate 9 for that of the signal S1 are delayed for a time Td since few response delay exists in the NOT gate 9. Therefore, the output signal S3 of an exclusive OR gate 7 goes to logic L within the range of the response delay time Td of the NOT gate 9. When the output signal S4 of two-input AND gate 5 is set at logic H, a switching transistor 4 is turned on. Meanwhile, the output signal S5 of the two-input AND gate goes to the logic L, and the power transistor 3 for discharge control is turned off.

Description

[Detailed Description of the Invention] [Industrial Application Field J] The present invention relates to a power transistor circuit for expanding and contracting a piezoelectric element, etc. by controlling charging and discharging of the piezoelectric element. The present invention relates to a constant conduction prevention circuit for performing υ control so that when a power transistor and a discharge control power transistor are alternately controlled to switch, both transistors are not turned on at the same time even momentarily.

[Conventional Technique Ifi] A conventional power transistor circuit for charging and discharging a piezoelectric element υ110 for driving the opening and closing of a needle valve of a fuel injection device disclosed in, for example, Japanese Unexamined Patent Publication No. 59-58129 is shown in FIG. As shown, PNP power transistor Q
The collector of NPN power transistor Q4 is connected to the collector of NPN power transistor Q4, and a piezoelectric element 120 is connected between the connection point of both collectors and ground. Further, while a voltage VDD from a fil source circuit (not shown) is applied to the emitter of the PNP power transistor Q2,
The emitter of NPN power transistor Q4 is connected to ground. Therefore, the PNP type power transistor Q2 is controlled to be turned on, and the NPN type power transistor Q2 is controlled to be turned on.
4 is turned off, the voltage VDD is applied to the piezoelectric element 120, and the piezoelectric element 120 is charged. On the other hand, the PNP type power transistor Q2 is controlled off, and the
When controlled by the power transistor Q4, the piezoelectric element 1
The charges charged in the transistor Q20 are discharged through the NPN power transistor Q4. That is, when the above charge/discharge control is performed, the piezoelectric element 120 expands and contracts in synchronization with the above charge/discharge. As described above, the PNP type power transistor Q2 has a function as a charge control power transistor, and the NPN type power transistor Q4 has a function as a discharge control power transistor.

In addition, in order to perform charge/discharge control as described above, the PN
A switching control circuit is provided for switching the P-type power transistor Q2 and the NPN-type power transistor Q4. As shown in the figure, the switching control circuit includes a not gate ICI which inputs an external control signal, inverts this signal and outputs it, and divides the output signal of this not gate IC1 by resistors R1 and R2. An NPN switching transistor Q1 inputs a signal obtained by dividing the output signal of the gate ICI into its base.
A P-type switching transistor Q3 is provided. Note that the NPN switching transistor Q1 and the PNP switching transistor Q3 are
It is provided to drive the NPN type power transistor Q2 and the NPN type power transistor Q4, and since the output signal of the not game h I C1 has an extremely small output current, it is directly connected to the above power transistor Q2,
Since Q4 cannot be driven, the power transistors Q2 and Q4 are driven by the signal amplified by the NPN switching transistor Q1 and the PNP switching transistor Q3.

Problems to be Solved by the Invention] In the conventional power transistor circuit described above, if the control signal a input from the outside to the NOT gate ICI is a pulse signal as shown in FIG.
If there is a difference in response between the N-type switching transistor Q1 and the PNP-type switching transistor Q3, the signal applied to the base of the PNP-type power transistor Q2 will change as shown in FIG. 7 (2) and (3). Then,
A timing difference occurs between the signal C and the signal C applied to the base of the NPN power transistor Q4.

The timing at which the PNP power transistor Q2 is turned on is when the signal C is in the logic rLJ state, and the timing at which the NPN power transistor Q4 is turned on is when the signal C is in the logic rHJ state. be. Therefore, as shown in FIG. 7(4), the above signal is logically r
LJ and when the signal @C is at the logic rHJ timing, the PNP type power transistor Q2 and the NP
Both N-type power transistors Q4 are turned on, and a large current from the power supply is directly applied to the PNP-type power transistor Q2.
Since the current flows to the ground through the NPN power transistor Q4, there is a problem in that the PNP power transistor Q2 and the NPN power I transistor Q4 are destroyed.

This problem occurs in the junction type PNP and NPN as described above.
This problem occurs not only in power transistors but also in MO8 field effect power transistors (MOSFETs).

Therefore, in the present invention, even if there is a slight deviation in the response characteristics of the switching control circuit or the charge/discharge control power transistor, the power 1 transistor is prevented from being turned on at the same time, and damage caused by excessive current is prevented. The technical problem to be solved is to prevent this.

[Means for Solving Problem 11] The technical means for solving the above problem is that when the charging control power transistor is controlled to be turned on, the load connected to the charging control power transistor is In a power transistor circuit in which a discharge current is passed from the load when the charge control power transistor is turned off and the discharge control power transistor is turned on after a charging current is passed, The charge control power transistor and the discharge control power transistor are turned on and off alternately according to the signal! A logic circuit for preventing the charging control power transistor and the discharging control power transistor from being turned on simultaneously is connected to the ζth switching control circuit.

[Function] In the above power transistor circuit, a logic circuit connected to a switching control circuit for alternately turning on and off the charging control power transistor and the discharging control power transistor according to an external control signal controls the charge control power transistor circuit. The power transistor and the discharge control power transistor are prevented from being turned on at the same time,
Destruction of the charge control power transistor and the discharge control power transistor due to excessive current from the power source is prevented.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a piezoelectric element control circuit of the first embodiment using a MOSFET (metal oxide semiconductor field effect transistor). This piezoelectric element 1 is used to drive a needle valve of a fuel injection device, for example. A needle valve (not shown) is driven by expanding and contracting the piezoelectric element 1 through charging and discharging control.In other words, the piezoelectric element 1 expands depending on the state of charge, and when the charged charge is discharged, it is discharged. It has the characteristic of shrinking depending on the condition.

As shown in FIG. 1, one terminal of the piezoelectric element 1 is connected to the drain D of a charging control power transistor 2CP channel MO8FET for supplying a charging current to the piezoelectric element 1, and Drain D of the discharge control power transistor 3 (N-channel O8FET) for passing a discharge current when discharging charges
are connected. Further, the other terminal of the piezoelectric element 1 is grounded. A drive power supply voltage VDD from a power supply (not shown) is applied to the source S and substrate SU of the power i-transistor 2 for charge control. On the other hand, the source S and substrate SU of the discharge control power transistor 3 are grounded. As mentioned above, 71
i, ll The Ill power transistor 2 is a P-channel MO8FET, and the discharge control power transistor 3 is an N-channel O8FET. Therefore, the charge control power transistor 2 is turned on when the signal applied to the gate G is logic rLJ, while the discharge control power transistor 3 is turned on when the signal applied to the gate G is logic rHJ. It turns on when

A train D of switching transistors 4 for driving the charge control power transistor 2 is connected to the gate G of the charge control power transistor 2 via a resistor 5A. The source S and substrate SU of the switching transistor 4 are grounded.

Further, the drive power supply voltage VDD is applied to the gate G of the charging control power transistor 2 via a resistor 5B. Note that the switching transistor 4 is an N-channel O8FET, and therefore turns on when the signal applied to the gate G is logic rHJ.

The gate G of the switching transistor 4 is connected to the output terminal of the two-power AND gate 5, and the gate G of the discharge ill all power transistor 3 is connected to the output terminal of the two-power AND gate 5.
It is connected to the output terminal of the two-man power AND gate 6. One input terminal of each of the two-person AND gate 5 and the two-person AND gate 6 is directly connected, and the output terminal of the exclusive-OR gate 7 is connected to this connection point. Further, each of the two input terminals of the exclusive OR gate 7 is connected to the input terminals of the two-person AND gate 5 and the two-person AND gate 6, respectively. One input terminal of the exclusive OR gate 7 is connected to a control signal input terminal 8 into which an external control signal is input.
The other input terminal of 7 is connected to the output terminal of knot gate 9. Further, the input terminals of the not games 1 and 9 are connected to the control signal input terminal 8.

In the piezoelectric element control circuit connected as described above, a pulse-like signal qS1 as shown in FIG. When applied, the output signal S2 of the knot gate 9 becomes a signal as shown in FIG. 2(2). At this time, since there is some response delay in the not gate 9, the timings of the falling and rising edges of the signal S2 are delayed by the time Td relative to the timings of rising and falling edges of the signal S1.

On the other hand, in the exclusive OR gate 7, as shown in FIG.
”, or if both are logic rLJ, the output signal is logic r
Therefore, the output signal S3 of the exclusive OR gate 7 becomes a NOT gate as shown in FIG. 2 (3).
The logic rLJ occurs within the response delay time Td of 9. Therefore, one input terminal of each of the two-man power AND gate 5 and the two-man power AND gate 6 has an exclusive OR gate 7.
Since the output signal S3 of is applied, the output signal S4 of the two-man powered AND gate 5 becomes as shown in FIG. 2 (4),
The output signal S5 of the two-man power AND gate 6 is shown in FIG. 2 (5).
It becomes as shown in .

The output signal S4 of the two-man power AND game 1 to 5 is the logic IN-I
When in the state J, the switching transistor 4 is in the on state, and as a result, the gate G of the charge control power transistor 2 becomes the logic rLJ, the transistor 2 is in the on state, and a charging current is applied to the piezoelectric element 1. is energized.

On the other hand, the output signal S5 of the two-man AND gate 6 is logic 1!
T! Since it is in the rLJ state, the f11 power control power transistor 3 is in the off state.

Figure 2 (4) 1. and the output signal S4 of the two-person AND gate 5 and the two-person AND gate as shown in FIG. 2 (5)]
・Since the output signals 85 of 6 do not become logic rHJ,
Both the charge control power transistor 2 and the discharge control power transistor 3 are turned on.

not be in a blank state. That is, the power transistor 2 for charge control and the power transistor 3 for discharge control are not simultaneously energized and destroyed.

In the above explanation, the control timing was explained in consideration of the response delay of the 1-game i to 9, but in reality, the 2-man-powered AND gate 5, 2-man-powered AND gate 6,
And the exclusive or gate 7 also has a response delay. Figure 2 (6), Figure 2 (7), and Figure 2 (8) are the timings at which the responses of the above 2-man-powered AND gate 5, 2-man-powered AND game 1-6, and exclusive or gate 7 were made last time. In the charts, Figure 2 (6) corresponds to Figure 2 (3), Figure 2 (7) corresponds to Figure 2 (4), and Figure 2 (8) corresponds to Figure 2 ( Corresponds to 5). In this case, two-manpower AND gate 5 and two-manpower AND gate 6
If the difference in response characteristic variation between them is within the range of time Td, both the output signals S4 and S5 of the two ant games 1-5 and 6 will not become logic rHJ. Therefore, the power transistor 2 for charge control and the power transistor 3 for discharge control titJ
It was instantaneous and the power was turned on at the same time, and it was a disaster! There's nothing to do.

Incidentally, since the two-man powered AND gate 5 and the two-man powered AND gate 6 have the same IC package inside the shell, the difference in variation in response characteristics is very small.

Next, a second practical example of the present invention will be explained.

FIG. 4 shows the piezoelectric element u1 tI11 circuit of the second embodiment, and FIG. 5 is a timing chart of the piezoelectric element control circuit.

The piezoelectric element control circuit shown in FIG. 4 is the same as the piezoelectric element control circuit shown in FIG. 1 explained in the first embodiment except for the two-manual AND gate 6, and the other elements used are the piezoelectric element shown in FIG. 1. The elements used are the same as those used in the control circuit, and the explanatory numbers of the respective elements used are the same as in FIG. Therefore, the output signal of the NOT gate 9 is applied to the input terminal of the exclusive OR gate 7 as in the first embodiment, while
The discharge control power 1 is applied directly to the gate 1-G of the transistor 3.

In the piezoelectric element control circuit connected as described above, a pulse-like signal S11 as shown in FIG. When applied to 8, knot gate 9
The output signal 812 becomes a signal as shown in FIG. 5(2). At this time, since there is a slight response delay in the not gate 9, the timings of the falling and rising edges of the signal 812 are delayed by the time Td relative to the rising and falling timings of the signal 811. Figure 5 (
3) is the output signal S1 of exclusive or games 1 to 7.
3, during the response delay time Td of the NOT gate 9, the output signal 813 of the exclusive OR gate 7 is Logic 1! I! It becomes rLJ. FIG. 5(4) is a timing chart of the output signal 814 of the two-man AND gate 5, and the output signal 814 is composed of the signal 811 and the output signal 8 of the exclusive OR gate 7.
13 are both in the logic rHJ state, the logic rHJ occurs.

In the piezoelectric element control circuit as described above, a charging side power transistor 2 and a discharging control power transistor 3 are used.
The timing at which the gate becomes simultaneously energized and destroyed is when the output signal 812 of the not gate 9 and the output signal 814 of the two-man AND gate 5 are both in the logic rHJ state, as shown in FIG. 5 (2). , as is clear from FIG. 5(4), the output signal 312 of the gate 9 and the two-person gate 5
The output signals 814 of both are controlled so that they do not go to the logic rHJ state.

In the above explanation, the control timing has been explained in consideration of the nearness of the response of the knot gate 9, but in reality, there is also a delay in the response of the two-player gate 5 and the exclusive or games 1 to 7. However, even if there is a response delay in the two-man AND gate 5 and the exclusive-OR gate 7, it can be compensated for in the same manner as in the first embodiment.

[Effects of the Invention] As described above, according to the present invention, when the charge control power transistor is controlled to be turned on, after the charge current from the power supply is applied to the load connected to the charge control power transistor, , in a power transistor circuit that causes a discharge current to flow from the load when the discharge side power transistor is controlled to be turned on while the charging control power i-transistor is controlled to be turned off, the charging is performed according to an external control signal. A switching control circuit for alternately turning on and off the control power transistor and the discharge control power transistor includes logic for preventing the charge control power transistor and the discharge control power 1-transistor from being turned on at the same time. Since the circuits are connected, it is possible to prevent the charge control power transistor and the discharge control power transistor from being simultaneously energized and destroyed.

[Brief explanation of the drawing]

Fig. 1 is a piezoelectric element control circuit diagram of the first embodiment using a field effect power transistor, Fig. 2 is a timing chart of the piezoelectric element control circuit of Fig. 1, and Fig. 3 is an input circuit diagram of the exclusion 1 OR gate. Output signal state diagram, FIG. 4 is a piezoelectric element control circuit diagram of the second embodiment, FIG. 5 is a timing chart diagram of the piezoelectric element control circuit of FIG. 4, and FIG. 6 is a conventional piezoelectric element control circuit diagram. FIG. 7 is a timing chart of the piezoelectric element control circuit of FIG. 6. 1...Piezoelectric element 2...Power transistor for charging control 3...tli
l Discharge control transistor 4... Switching transistor 5... Two-person AND gate 6... Two-person AND gate 7... Exclusive or gate 9... Not gate

Claims (1)

[Claims] When the charging control power transistor is turned on,
After applying a charging current from the power supply to the load connected to the charge control power transistor, when the discharge control power transistor is turned on while the charge control power transistor is turned off, the load In a power transistor circuit in which a discharge current is passed through a switching control circuit for alternately turning on and off the charging control power transistor and the discharging control power transistor according to an external control signal, the charging control power 1. A simultaneous energization prevention circuit for a power transistor circuit, characterized in that a logic circuit for preventing a transistor and the discharge control power transistor from being turned on at the same time is connected thereto.