JPH0361373B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a D/A conversion circuit that converts a multi-channel digital signal such as a stereo signal into an analog signal.

(Prior art) In digital equipment such as compact disc (CD) players, digital data of multiple channels such as stereo left and right signals are arranged in series, and when converting this to DA, it is necessary to correctly match the phase between each channel. There is a need.

For this purpose, in the past, each channel data was converted into parallel data, and independent D/A converters were used to drive them with the same clock to perform D/A conversion. However, this requires the use of multiple expensive D/A converters.

Also, using one DA converter, serial data of stereo left and right signals can be D/A in the same order.
In the case where an analog stereo signal is obtained by extracting the stereo left and right signals using a sample and hold circuit, the D/A
To be converted, one channel is delayed in time by half a cycle of the sample period. For this reason, another stage of sample and hold circuit is added to the more advanced channel, and the phase is adjusted by delaying the signal by half a cycle.

(Problems to be solved by the invention) However, in such a D/A conversion circuit,
Although the phase shift is eliminated, one channel has an additional sample-and-hold circuit, which increases distortion and noise and tends to cause unbalanced characteristics between channels. In view of these points, the present invention provides a digital-to-analog conversion circuit that sequentially processes digital signals of a plurality of channels using one D/A converter and does not cause a phase difference between the channels.

(Means for Solving the Problems) For this purpose, the present invention provides a digital filter means for oversampling the parallel digital data of multiple channels, and filters the digital data at the relevant time in a predetermined channel order from the oversampled parallel digital data. are sequentially extracted to obtain aligned serial digital data, which is added to one D/A converter to obtain a serial analog data string, which is then added to the plurality of sampling circuits corresponding to the plurality of channels mentioned above for sequential sampling. Then, each analog data for the plurality of channels is reproduced.

(Operation) As mentioned above, since the serial data arranged in sequence is assigned by estimating the true data at that time, this is converted into a serial analog data string by one D/A converter. , by sampling and holding this at the phase of each channel, it is possible to demodulate the analog data of each channel.

(Embodiment) FIG. 1 shows an embodiment in which the present invention is applied to a digital-to-analog conversion circuit that obtains an analog signal from stereo left and right parallel digital signals.

In the figure, stereo left and right digital signals L(D) and R(D) are applied to 2x oversampling digital filters 1 and 2, and their outputs are D/A converted via a parallel-to-serial converter 3. Added to container 4. The output of the D/A converter 4 is applied to sample and hold circuits 5 and 6, where it is sampled and held by sample and hold signals f and g from the sampling signal generator 7 to produce left and right analog signals L(A) and R. Converted to (A).

The operation of the above configuration will be explained using the waveform diagram of each part in FIG. FIG. 2 shows the case where the input digital signals L(D) and R(D) in FIG. The output waveform indicated by ~k is shown.

Waveforms a and b are stereo left and right signal waveforms 10
The data values 11 ₁ and 11 at each sampling time of the parallel digital data L(D) and R(D) obtained by sampling at the basic sampling period T
₂ ,...11 _o . These digital signals L(D) and R(D) are passed through digital filters 1 and 2.
is oversampled by a factor of 2. As a result, data 12A ₁ , 12B 1 , ₁₂ which is almost the same as doubling the basic sampling frequency by interpolating the intermediate data of each basic sampling period as shown in Fig. 2c and d, are obtained.
A ₂ , 12B ₂ , . . . 12B _o are obtained. Parallel data c with twice this sampling frequency,
d is converted into serial data by the parallel/serial converter 3. In this case, in the first half of the basic sampling synchronization T, data 12A ₁ , 12A ₂ ,
12A ₃ ,...12A _o are extracted and assigned, and in the second half, the data 12B ₁ , 12B ₂ , 12B ₃ ...12B _o of the output d from the digital filter 2 for the right channel are extracted and assigned.
Extract and assign. That is, the input digital data L(D) is used as it is for the left channel, and the intermediate data at the sampling interval generated by the digital filter is used for the right channel, and these left and right data are converted into serial data.

In this way, serial data 12A _1L , 12B _1R , 12A _2L ,...
12A _oR is obtained. This serial data is D/
D/A conversion is performed by the A conversion circuit 4, and the analog data of the left and right channels are output alternately, so that serial analog data can be obtained. This analog data is sampled and held by sampling and holding circuits 5 and 6. In this case, the sample and hold pulses f and g for the left and right channels are:
As shown in the figure, pulses 13 having a phase difference of 180° from each other,
14, from the left and right serial analog data of the D/A conversion circuit 4, the analog output L(A) for the left channel and the analog output L(B) for the right channel are extracted as waveforms h and k, respectively.

In the above embodiment, both the left and right channels were processed by the digital filter in order to make the delay times the same, but only the right channel was processed by the digital filter to obtain data 12B ₁ and 12B in the middle of the sampling interval shown in FIG. 2d. ₂ ...12B _o is generated, and this generated data is used as data for the right channel.For the left channel, a delay is given to compensate for the delay of the digital filter for the right channel, and it is used as data for the left channel, and these data for the left and right channels are It is of course possible to obtain serial data as shown in FIG. 2(e) by serially converting the data.

Further, the present invention is not necessarily limited to the case of a two-channel signal such as the above-mentioned stereo signal, but can be applied to a signal having any number of channels. For example, in the case of 4 channels, the sampling interval of the input digital signal is equally divided into four sections, and the digital data of the other three sections except the first one is estimated and calculated according to the delay amount of each section. Just convert it to serial data.

(Effects) As described above, according to the present invention, parallel digital data is converted into serial digital data with time delay corrected, and this is converted into serial analog data by one D/A conversion circuit. Since parallel analog data is obtained by sampling and holding the analog data for the left and right channels from the analog data, it is possible to obtain analog data without time delay by using only one D/A converter.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figures are waveform diagrams of various parts for explaining the operation. 1, 2...Digital filter, 3...Parallel/serial conversion circuit, 4...D/A converter,
5, 6... Sampling hold circuit, 7... Sampling signal generator.

Claims (1)

[Claims] 1 digital filter means for oversampling parallel digital data of a plurality of channels, means for extracting and arranging the current digital data in a predetermined channel order from the oversampled parallel digital data, and obtaining serial digital data; A digital-to-analog conversion circuit comprising: a D/A converter for converting data into serial analog data; and a sampling means for extracting analog data corresponding to the order of each channel from the analog data to each channel.