JPH0361722U - - Google Patents
Info
- Publication number
- JPH0361722U JPH0361722U JP12208389U JP12208389U JPH0361722U JP H0361722 U JPH0361722 U JP H0361722U JP 12208389 U JP12208389 U JP 12208389U JP 12208389 U JP12208389 U JP 12208389U JP H0361722 U JPH0361722 U JP H0361722U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- comparator
- expected value
- reference voltage
- comparison
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Description
第１図は本考案に係るコンパレータ回路の構成
図、第２図は第１図のコンパレータ回路のタイミ
ングチヤート、第３図は従来のコンパレータ回路
の構成図、第４図は従来のコンパレータ回路のタ
イミングチヤートである。
１……信号出力回路、４……比較回路、５……
判定回路、７……リフアレンス電圧切り替えスイ
ツチ、８……コンパレータ。
Fig. 1 is a block diagram of a comparator circuit according to the present invention, Fig. 2 is a timing chart of the comparator circuit of Fig. 1, Fig. 3 is a block diagram of a conventional comparator circuit, and Fig. 4 is a timing chart of a conventional comparator circuit. It's a chat. 1...Signal output circuit, 4...Comparison circuit, 5...
Judgment circuit, 7... Reference voltage changeover switch, 8... Comparator.
Claims (1)
り替えるリフアレンス電圧切り替え回路と、 この切り替え回路によつて選択されたリフアレ
ンス電圧と入力信号を比較し、比較結果をハイ側
とロー側の２つの出力信号で出力する差動出力コ
ンパレータと、 このコンパレータからの２つの出力信号と、期
待値を入力し、期待値のレベルに応じて２つの出
力の一方を選択し、期待値と比較する比較回路と
、 判定ストローブのタイミングで比較の結果をラ
ツチする判定回路と、 を有することを特徴とするコンパレータ回路。[Claims for Utility Model Registration] A reference voltage switching circuit that switches reference voltages having different levels; a reference voltage selected by the switching circuit is compared with an input signal, and the comparison results are used for high-side and low-side A differential output comparator that outputs two output signals, input the two output signals from this comparator and the expected value, select one of the two outputs according to the level of the expected value, and compare it with the expected value. A comparator circuit comprising: a comparison circuit; and a determination circuit that latches the comparison result at the timing of a determination strobe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12208389U JPH0756514Y2 (en) | 1989-10-18 | 1989-10-18 | LSI test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12208389U JPH0756514Y2 (en) | 1989-10-18 | 1989-10-18 | LSI test system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0361722U true JPH0361722U (en) | 1991-06-17 |
| JPH0756514Y2 JPH0756514Y2 (en) | 1995-12-25 |
Family
ID=31670099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12208389U Expired - Lifetime JPH0756514Y2 (en) | 1989-10-18 | 1989-10-18 | LSI test system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0756514Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000304818A (en) * | 1999-04-21 | 2000-11-02 | Advantest Corp | Semiconductor test device |
-
1989
- 1989-10-18 JP JP12208389U patent/JPH0756514Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000304818A (en) * | 1999-04-21 | 2000-11-02 | Advantest Corp | Semiconductor test device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0756514Y2 (en) | 1995-12-25 |
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