JPH0361759U - - Google Patents
Info
- Publication number
- JPH0361759U JPH0361759U JP1989123307U JP12330789U JPH0361759U JP H0361759 U JPH0361759 U JP H0361759U JP 1989123307 U JP1989123307 U JP 1989123307U JP 12330789 U JP12330789 U JP 12330789U JP H0361759 U JPH0361759 U JP H0361759U
- Authority
- JP
- Japan
- Prior art keywords
- screen
- signal
- sub
- memory
- synchronization signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Studio Circuits (AREA)
Description
第１図及び第２図は本考案の映像処理装置の１
実施例を示し、第１図はブロツク図、第２図ａ，
ｂは動作説明用のタイミングチヤート、第３図は
従来例のブロツク図である。
８ｂ……メモリ制御回路、１５ｂ……クロマデ
コーダ回路、１８……メモリ、２５……単安定マ
ルチバイブレータ、２６……同期信号作成回路、
２７……書込基準切換スイツチ、２９……輝度入
力切換スイツチ。
Figures 1 and 2 show one of the video processing devices of the present invention.
An example is shown, FIG. 1 is a block diagram, FIG. 2 a,
b is a timing chart for explaining the operation, and FIG. 3 is a block diagram of a conventional example. 8b... Memory control circuit, 15b... Chroma decoder circuit, 18... Memory, 25... Monostable multivibrator, 26... Synchronous signal generation circuit,
27...Writing standard changeover switch, 29...Brightness input changeover switch.
Claims (1)
のモード設定時、子画面用の映像信号の同期信号
を基準にしたメモリの書込みと親画面用の映像信
号の同期信号を基準にした前記メモリの読出しと
により前記子画面用の映像信号を圧縮した１又は
複数の子画面信号を形成し、前記親画面用の映像
信号の１又は複数の子画面挿入位置に前記各子画
面信号を挿入した合成画面の映像信号を形成する
映像処理装置において、 同期信号を自走発振形成する同期信号作成回路
と、 前記モード設定時に前記メモリの書込みの基準
信号を初期の一定期間前記作成回路の出力信号に
保持し前記一定期間後に前記子画面用の映像信号
の同期信号に切換える書込基準切換スイツチと、 前記書込基準切換スイツチに連動して前記一定
期間前記メモリの入力信号を黒レベル画面用の直
流信号に保持する書込入力制御手段と、 前記一定期間前記メモリの読出し又は前記各子
画面信号の挿入を禁止ゲート手段と を備えた映像処理装置。[Claim for Utility Model Registration] When picture-in-picture screen or multi-screen mode is set, memory writing is based on the synchronization signal of the video signal for the child screen and the synchronization signal of the video signal for the main screen is based on the synchronization signal of the video signal for the main screen. One or more sub-screen signals are formed by compressing the video signal for the sub-screen by reading out the memory, and each sub-screen is inserted into the one or more sub-screen insertion positions of the video signal for the main screen. A video processing device that forms a video signal of a composite screen into which a signal is inserted, comprising: a synchronization signal creation circuit that creates a free-running oscillation of a synchronization signal; and a synchronization signal generation circuit that generates a reference signal for writing in the memory for an initial certain period of time when setting the mode. a writing reference changeover switch that maintains the output signal at the output signal of the memory and switches it to a synchronization signal of the video signal for the sub-screen after the certain period of time; A video processing device comprising: a write input control means for holding a DC signal for a screen; and a gate means for prohibiting reading of the memory or insertion of each of the child screen signals for the certain period of time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989123307U JPH0361759U (en) | 1989-10-20 | 1989-10-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989123307U JPH0361759U (en) | 1989-10-20 | 1989-10-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0361759U true JPH0361759U (en) | 1991-06-17 |
Family
ID=31671292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989123307U Pending JPH0361759U (en) | 1989-10-20 | 1989-10-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0361759U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6218181A (en) * | 1985-07-16 | 1987-01-27 | Toshiba Corp | Memory access circuit |
-
1989
- 1989-10-20 JP JP1989123307U patent/JPH0361759U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6218181A (en) * | 1985-07-16 | 1987-01-27 | Toshiba Corp | Memory access circuit |
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