JPH0362094A - Gradation display driving circuit of active matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide gradation reproducibility and to reduce electric power consumption by providing an analog/digital converting circuit and a pulse width modulating driver. CONSTITUTION:The A/D converting circuit 40 converts an analog video signal to a digital video signal and applies the digital video signal to the pulse width modulating driver 60. The pulse width modulating driver 60 activates the data signal at the timing coinciding with the activation period of a scanning signal and supplies the data signal via an active element to a liquid crystal cell so that the gradation display of good reproducibility is executed. The pulse width modulating driver 60 acts to lower a driving frequency by executing the data shift in the data output period by the latch function thereof. The driving with the low-driving frequency is possible in this way and the electric power consumption is reduced.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a gradation display drive circuit for an active matrix liquid crystal display device in which an active element such as a transistor for driving a liquid crystal is arranged in each pixel. be.

(Prior art) Conventional technologies in this field include, for example, the Journal of the Television Society, Sei [1] (1988) p.

There was one described in 23-29.

In general, there are two types of liquid crystal display devices: an active matrix type in which a thin M element such as a transistor for driving the liquid crystal is arranged in each pixel, and a simple matrix type in which the liquid crystal material of each pixel is directly time-divisionally driven from the outside. Separated. Further, there are transistors and bidirectional diodes as active matrix elements, and among these, they are classified into several types depending on the material used.

In conventional active matrix liquid crystal display devices,
The gradation display method includes, for example, a voltage modulation method as described in the above-mentioned document. An example is shown in FIG.

FIG. 2 is a basic configuration diagram showing a conventional three-terminal active matrix type liquid crystal display device.

This liquid crystal display device includes a liquid crystal panel 10, and the liquid crystal panel 10 includes a horizontal X driver 20 that outputs a display data signal, and a vertical Y driver 20 that outputs a scanning signal.
A driver and driver 21 are connected. The liquid crystal panel 10 is
A plurality of data electrodes (also referred to as source lines) 1-1 to 11-4... connected to the X driver 20 and a plurality of scan electrodes (also referred to as gate lines) connected to the Y driver 21
121 to 12-4... Data electrodes 11-1 to 11-4... and scanning electrodes 12-1 to 12-
A switching element, for example, an amorphous Si thin film transistor (hereinafter referred to as TPT) 13 and a liquid crystal cell 14 are provided at each intersection with 4.... The source of TPT'13 is connected to the data electrode, the gate to the scanning electrode, and the drain to the liquid crystal cell 14, respectively.

A conventional gradation display drive circuit in such a liquid crystal display device is configured as follows.

FIG. 3 shows the data signal VS (=VS1.VS2.....) which is the output of the X driver 20 in FIG.
The scanning signal VG (=VG1.V
G2. -=, VGn). The scanning signal VG is a signal in which an ON signal (activation signal) for 1 horizontal period is repeated every vertical period.The data signal S is a voltage signal corresponding to the video signal, and the scanning signal VG is ON. X driver 20 in accordance with the timing of
is output from. This data signal VS is generated by the circuits shown in FIGS. 4 and 6.

FIG. 4 is a block diagram showing an example of the configuration of a conventional video signal processing circuit.

This video signal processing circuit processes analog video signals of R (red), G (green), and B (blue).
This is a circuit that adapts to the optical characteristics of the liquid crystal shown in FIG. 5 and converts it into a signal that can be driven by alternating current. In this circuit, R
, G, and B analog video signals are sent to the amplifier 30.
After amplification by -1 to 30-3, phase division circuit 31-1 to
31-3, a positive polarity video signal (same polarity as the input video signal) and a negative polarity video signal (opposite polarity to the input video signal) are generated.Flip-flop U
gJHjJ (hereinafter referred to as FF) 33 outputs a signal whose polarity is inverted with the period of the vertical synchronization signal from a switching circuit 32-↓~
Output to 32-3. Then, the output switching circuit 32-l~
32-3 selects positive or negative polarity and outputs video signals VIDEOA, VIDEOB, VIDE of one polarity.
Output OC.

Here, video signals VIDEOA, VIDEOB, VI
DEOC adjusts the contrast so that its amplitude corresponds to the voltage width ΔV between the threshold voltage vth at which the transmittance rises and the voltage Vsat at which the transmittance saturates in the electro-optical characteristics of the liquid crystal shown in FIG. Further, the brightness is adjusted so that the lower end level of the video output matches vth. Such video signals VIDEOA, VIDEOB.

VIDEOC is input to the circuit of FIG.

FIG. 6 is a circuit diagram showing a configuration example of the X driver 20 in FIG. 2, and FIG. 7 is an operation waveform diagram of FIG. 6.

This X driver 20 includes a 60-bit dynamic shift register 21. It is composed of a level shifter 22, a 60-inch switch 23, a 60-inch capacitor 24, a 60-inch buffer 25, and a current source 26. In addition, COM
is a common terminal, HO60 is a terminal, OE is an output enable signal, STH is a horizontal scanning start pulse, CPH is a horizontal shift clock, TST is a test signal, Vb, VBBI ~
VBB3. VDD and VSS are voltages, and VSI to VS60 are data signals.

In this X driver 20, the ON output of the 60-bit dynamic shift register 21 is sequentially shifted by the horizontal shift clock after the horizontal scanning start pulse STH is input. The output of the shift register 22 is applied to the switch 23 via the level shifter 22, and the on state of the switch 23 is sequentially scanned. During the sample and hold period, when the switch 23 is turned on, an amount of charge proportional to the video signals VIDEOA, VIDEOB, and VIDEOC is accumulated (sampled and held) in the capacitor 24 as a sample and hold circuit.

After sample and hold for a predetermined number of pixels is completed, the output enable signal OE becomes “°H” during the data output period.
When the level is reached, the video signals VIDEOA and VIDE
OB, data signal VSI with voltage proportional to VIDEOC
~VS60 is output from the buffer 25. Therefore,
The sample hold period and data output period must not overlap in time. For example, ■Horizontal period 63. In bow μS, to output definite data for 20 μs, the sample hold period is 43.5 μs.
The following is true. Assuming that the number of sampling data within one horizontal period is 640, the frequency of the horizontal shift clock CPH is 640/43°5614.7 MHz or more.

Data signal VS1~ output from this X driver 20
VS60 is connected to the data electrodes 11-1 to 11-4 in FIG.
... is applied to the source of each TPT 13. Further, at the gate of each TPT 13, scanning electrodes 12 to l to
12-4... via scanning signals VGI to VG4...
are applied respectively.

In FIG. 2, when the scanning signal VG is applied to the gate of the TFT 13, the source and drain of the TPT 13 are turned on, and the data signal
S is applied to the liquid crystal cell 14. This operating waveform diagram is the 8th
This is shown in Figures (a) and (b).

As shown in FIGS. 8(a) and 8(b), for example, when a data signal VSI is applied to the source of the TFT 13, a charge proportional to the voltage of the data signal VSI is accumulated in the liquid crystal cell 14 with a certain time constant. To go. When the scanning signal VG turns off, the source and drain of the TPT13 become non-conductive, the charge accumulated up to that time is held, and the voltage of the data signal VSI proportional to the charge is applied to the liquid crystal cell 4. be done. The same applies to the data signal S2 of other voltages.

Figure 9 is an electro-optical characteristic diagram of the liquid crystal.As shown in this figure, the relationship between the video signal voltage and the relative transmittance of the liquid crystal is not proportional; becomes saturated.

(Problems to be Solved by the Invention) However, in the gradation display drive circuit composed of the X driver 20, Y driver 21, and video signal processing circuit shown in FIGS. 2, 4, and 6, the following There were issues like this.

(i) As shown in Figure 9, the relationship between the video signal voltage and the relative transmittance of the liquid crystal, that is, the electro-optical characteristics of the liquid crystal, is
There is a problem that there is no proportional relationship and the transmittance is saturated at dark and bright levels, resulting in insufficient reproducibility of gradation expression at dark and bright levels, resulting in deterioration of image quality.

(ii) As shown in FIG. 7, a sample hold period and a data output period must be provided independently.

Therefore, in the dynamic shift register 21 of FIG. 6, the horizontal shift clock CPH for shifting data is
It is necessary to increase the driving frequency. However, as the drive frequency increases, the power consumption generally increases, so there is a problem in that the power consumption of the gradation display drive circuit is large. Therefore, technically satisfactory results could not be obtained.

The present invention solves the problems that the prior art had, such as insufficient gradation reproducibility at dark and bright levels.
The present invention provides a gradation display drive circuit for an active matrix liquid crystal display device that solves the problem of high power consumption due to high drive frequency.

(Means for Solving the Problems) In order to solve the above problems, a first invention provides a liquid crystal panel in which active elements and liquid crystal cells connected to orthogonal locations of scanning electrodes and data electrodes are arranged in a matrix. On the other hand, gradation display driving of an active matrix liquid crystal display device that supplies a scanning signal to the scanning electrode and a data signal with a predetermined pulse width to the data electrode to drive gradation display of the liquid crystal panel. The circuit includes an analog/digital conversion circuit (hereinafter referred to as an A/D conversion circuit) that converts an analog video signal to a digital video signal and outputs it, and a clock signal for shifting and latching the digital video signal and for controlling gradation. and a pulse width modulation driver for generating a data signal having a pulse width having an activation period coinciding with the activation period of the scanning signal and supplying the data signal to the data electrode.

A second invention provides the pulse width modulation driver of the second invention,
Shifting and latching the digital video signal, pulse width modulating the digital video signal based on a gradation control clock signal, and generating a data signal having a pulse width having an inactivation period that coincides with an inactivation period of the scanning signal. The structure is such that the data is supplied to the data electrodes.

A third invention is based on the first or second invention, and includes a counter that performs a counting operation using a clock pulse of a constant period and outputs a plurality of frequency-divided pulses, and a counter that outputs a plurality of frequency-divided pulses, and stores data at an address specified by the output pulse of the counter. The output memory is configured to generate a gradation control clock signal input to the pulse width modulation driver.

A fourth invention is based on the third invention, wherein the data sets the pulse width of the gradation control clock signal for each gradation level so that the transmittance of the liquid crystal cell and the video signal are approximately proportional to each other. , is stored in the memory in advance.

(Operation) According to the first invention, since the gradation display drive circuit is configured as described above, the A/D conversion circuit converts an analog video signal into a digital video signal, and pulse width modulates the digital video signal. The pulse width modulation driver activates the data signal at a timing that matches the activation period of the scanning signal, supplies the data signal to the liquid crystal cell via the active element, and generates a highly reproducible signal. Furthermore, the pulse width modulation driver has a latch function that shifts data during the data output period to reduce the driving frequency.

The pulse width modulation driver in the second invention deactivates the data signal at a timing that coincides with the deactivation period of the scanning signal, and supplies the data signal to the liquid crystal cell via the active element. It works almost the same as invention 1.

In the inventions shown in FIGS. 3 and 4, the gradation level can be changed by changing the pulse width of the gradation control clock signal to improve reproducibility.

Therefore, the above problem can be solved.

(Embodiment) The first drawing is a block diagram of a main part of a gradation display drive circuit in an active matrix liquid crystal display device showing an embodiment of the present invention.

In this embodiment, the basic configuration of the active matrix liquid crystal display device is the same as that of the conventional one shown in FIG. In particular, in this embodiment, the A/D converter 40, clock generation circuit 50, and pulse width modulation driver 60 shown in FIG. 1 are provided in place of the X driver 20 shown in FIG. The Y driver 2 (2) shown in the figure constitutes a gradation display drive circuit.

A block diagram of the configuration of the A/D conversion section 40 is shown in FIG. 10, and a block diagram of the configuration of the clock generation circuit 50 is shown in FIG. 11.

The A/D converter 40 in FIG. 10 converts R, G, and B analog video signals into odd-numbered 4-bit digital video signals OD.
O~OD3 and even 4-bit digital video signal ED
This is a circuit that converts from O to ED3. This A/D converter 4
0 is composed of amplifiers 41-l to 41-3, an output switching circuit 42, and an A/D conversion circuit 843-1.43-2, and the output side of the A/D conversion circuit 43-1.43-2 is the It is connected to the pulse width modulation driver 60 in Figure i.

The clock generation circuit 50 in FIG. 11 is a circuit that generates a gradation control clock signal CPG, and has a clock generation circuit 51, and the output of the clock generation circuit 51 and the reset signal RT are sent to a binary up counter 52-1. It is connected to the. The output of the binary up counter 52-1 and the reset signal RT are connected to the binary up counter 52-2, and the binary up counter 52-1.52-
The output of 2 is connected to memory 53. The output of the memory 53 is connected to a buffer 55 via a multiplexer 54 for signal selection. Maltiff.

A resistor 56 is connected to the control signal terminals A, B, and C of the lexer 54.
and a switch circuit 57 are connected.

Gradation control clock signal C output from buffer 55
PG is supplied to pulse width modulation driver 60 of FIG.

Pulse width modulation driver 60 of FIG. 1 receives digital video signals EDO-ED3. This circuit outputs 80-bit data signals VS1 to vsso having pulse widths corresponding to ODO to OD3 to data electrodes 11-1 to 14 in FIG. 2.

This pulse width modulation driver 60 starts its operation in response to a horizontal scanning start pulse STA, and receives a horizontal shift clock C.
P generates digital video signals EDO to ED3. ODO
It has two 4-bit x 40 shift registers 61 and 62 that take in ~oD3, and on the output side of the shift registers 61 and 62 there is an 80-bit x 4 latch circuit &463, and a gradation control section 64.80 bits. level shifters 65 and 80 four-level drivers 66 are connected. The latch circuit 63 outputs the shift register 6 by the load signal LOAD.
This is a circuit that latches the output of 1.62.

The gradation control unit 64 receives the 4-bit output data (O to F in hexadecimal) of the latch circuit 63 and the gradation control clock signal C.
This circuit outputs a gradation signal S64 with a pulse width determined by PG, and is composed of a counter, a gate circuit, and the like. The level shifter 65 has a function of shifting the level of the gradation signal S64 using the switching signal DF.

The driver 66 has four levels of voltage V1. V3. V4. V
Based on EE, the output of level shifter 65 is driven to 80
There is a circuit that outputs bit data signals VSI to vsso.

In addition, VDD in Figure ■ is the power supply voltage, VSS is the ground potential,
END is a terminal for connecting to the next stage.

The operation of the gradation display drive circuit configured as above will be explained.

FIG. 12 shows the scanning signal VG (=VG1.VG2..., VGn) which is the output of the Y driver 21 in FIG. =VS1.VS2...vsso>.The scan 1 word VG is a signal that is repeated every vertical cycle, and its activated state (on state) is the same as that of the scan electrode 12 in FIG. -1-12-2→12-3
→... are sequentially scanned. A data signal (1)S is applied to the data electrodes 11-1 to 11-4, . . . in synchronization with the on-state timing of the scanning signal VG. Such a data signal VS is generated as follows.

In the A/D converter 40 of FIGS. 1 and 10, R,
The G and B analog video signals are amplified by amplifiers 41-■ to 41-3 in FIG.
For example, an R video signal is output from the output terminal outl, and a G video signal is output from the output terminal out2. After the R, G video signal is output, the B, R video signal -G
, B video signal - R, G video signal - . . . are output in this order. The video signals output from the output terminals outl and out2 are sent to each A/D conversion circuit 43-1, 43-2.
and each 4-bit odd digital video signal ODO
~OD3 and even digital video signal EDO~ED3
is converted to At this time, A/D conversion circuits 43-1, 43
2, the video signal input to the A/D conversion circuit 43
Amplifiers 4-1 to 41-3 are adjusted to fall within the dynamic range of -1.43-2.

The two 4-bit digital video signals ODO to OD3. When EDO to ED3 are input to the shift registers 61 and 62 in the first pulse width modulation driver 60, the pulse width modulation driver 60 operates as shown in the operational waveform diagram shown in FIG. I3.

That is, the shift registers 61 and 62 start operating in response to the horizontal scanning start pulse STA, and in accordance with the horizontal shift clock CP, the shift registers 61 and 62 output two 4-bit digital video signals E.
DO~ED3. Shift ODO to OD3. 4-bit digital video signals ED○ to ED3. ODO～O
When the shift of D3 is completed, the display data stored in the shift registers 61 and 62 is latched into the latch circuit 63 by the load signal LOAD. The latched 4-bit digital video signal is input to the gradation control section 64. The gradation control unit 64 receives input 4-bit data (1
A gradation signal S64 having a pulse width determined by a hexadecimal number of 0 to F> and a gradation control clock signal CPG is output to the level shifter 65.

Here, the gradation control clock signal CPG is generated by the clock generation circuit 50 shown in FIG.

That is, the clock pulse output from the clock generation port B51 in FIG. 1 is input to the binary up counter 52-1. Binary up counter 52-work and 52-
2 are connected in cascade, and a reset signal RT, which is the polarity of the load signal LOAD inverted, is input to the reset terminal R of the binary up counter 52-1.522.

The binary up counters 52-1, 52-2 count up using the clock from the clock generation circuit 51 using the reset signal RT as a reference, and output terminals A, B, C,
D outputs a plurality of frequency-divided pulses to address input terminals AO to A7 of the memory 53. The memory 53 outputs stored data from output terminals Ql to Q8 in accordance with designated addresses input to address input terminals AO to A7. The data stored in the memory 53 is set so that each output becomes a signal composed of 14 pulses within one cycle of the reset signal RT.

Outputs from output terminals Q1 to Q8 of memory 53 are input to input terminals X1 to X8 of multiplexer 54. On the other hand, the input signals of control terminals A, B, and C in the multiplexer 54 are determined by a switch 57. When the switch 57 is closed, the control terminals AB and C are grounded and II L 1
When the switch 57 is opened, the control terminals A, B, and C are pulled up to the power supply voltage VCC by the resistor 56 and become the "H" level. Depending on the state of the signals input to the control terminals A, B, and C, one of the input terminals X1 to X8 is selected and output from the output terminal Y. The output of the output terminal Y is output via the buffer 55 in the form of a gradation control clock signal CPG, and is sent to the gradation control section 64 in FIG.

Note that the load signal LOAD input to the latch circuit 63
also serves as a reset signal for the gradation signal output.

Next, the determination of the pulse width of the gray scale signal S64 in the gray scale control section 64 will be explained with reference to FIG. Incidentally, FIG. 4 is a gradation time chart of FIG. 11.

In the gradation control section 64, when the gradation signal S64 is reset by the load signal LOAD, the gradation signal S64
turns on. For example, when 4-bit data of "0'° in hexadecimal notation is input to the gradation control section 64, the gradation signal S64 is turned off. If 4-bit data of "1 part" is input in hexadecimal notation, the gradation signal S64 is turned off. When the load signal LOAD
The gradation signal 364 turns off with the l-th pulse of the clock signal CPG counting from the clock signal CPG, and the gradation signal S64 with a pulse width that turns on with the next load signal LOAD is output. Thereafter, in the same manner, a gradation signal 364 having a pulse width corresponding to the 4-bit data up to FTl in hexadecimal notation is obtained. Such a gradation signal S64 is inputted to a 4-level driver 66 via an 80-bit level shifter 65.
The data signals VS1 to VS80 for driving liquid crystal cells are converted and sent to data electrodes 11-1 to 11-4 in FIG. 2.

Here, since the latch circuit B63 is provided in the pulse width modulation driver 60 of FIG. 1, data can be shifted simultaneously during the data output period. Therefore, the entire one horizontal cycle period (for example, 63.5 μs) can be used for data shift time, and the drive frequency can be lowered to reduce power consumption. For example, if the number of transferred data is 640, 8 bits, or 2 data, can be transferred in one clock, so (640÷2)÷63.5=5
MHz.

In FIG. 2, the scanning signal VGI of the Y driver 2
, VG2. ... is the scanning electrode 12-1, 12-2...
・Apply an on-state voltage to the gate of the TFT 13 via. At this time, the source and train of the TPT 13 electrically connected to the scanning electrodes 12-1, 12-2, . . . become conductive. Data signals VSI, VS2 .・
... are data electrodes 11-1, 11-2. ... is applied to the source of the TFT 13. The timing of the scanning signal VG and the data signal VS is as shown in FIG. 15.

That is, the gradation control section 64 shown in FIG. 1 causes the time when the scanning signal VG is on to match the time when the data signal VS is on. For example, if the pulse width of the scanning signal VG is T
H, when the pulse width of the data signal VS is tl, the scanning signal V
The data signal VS is turned on at the same time that G is turned on.

At such timing, when the scanning signal VG is on and the data signal S is on, charges are accumulated in the liquid crystal cell 14 in FIG. 2 with a certain time constant. When the scanning signal VG is on and the data signal S is off, the charges accumulated in the liquid crystal cell 14 begin to be discharged.

Therefore, the amount of accumulated charge decreases with time. Thereafter, when the scanning signal VG is turned off, the TPT 13 becomes non-conductive, the charges accumulated up to that point are held, and the voltage V1 corresponding to the amount of charges continues to be applied to the liquid crystal cell 14.

Similarly, when the pulse width of the data signal VS is L2,
A voltage V2 corresponding to the pulse width is applied to the liquid crystal cell 4.

The relationship between the pulse width and the transmittance of the liquid crystal is as shown in the electro-optical characteristic diagram in FIG. Therefore, by determining the pulse width from the characteristics shown in FIG. 16, that is, in FIG.
As shown in the electro-optical characteristic diagram of FIG. 17, by writing data into the 14-bit 14-bit 1000, it is possible to create a proportional relationship between the video signal and the transmittance of the liquid crystal cell 14, resulting in a gradation with excellent reproducibility. You can get the display.

In addition, the control signal of the multiplexer 54 in the tarlock generation circuit 50 is changed by the switch 57, and the input terminals Xi, X2, .
. . , X8, or by changing the data in the memory 53, desired gradation characteristics can be obtained.

Next, another embodiment of the present invention will be described with reference to FIGS. 18 to 20.

In addition, FIG. 18 is another gradation time chart of FIG. 11,
FIG. 19 is a timing diagram of scanning signals and data signals, and FIG. 20 is an electro-optical characteristic diagram of liquid crystal.

Determination of another pulse width of the gradation signal S64 in the gradation control section 64 shown in FIG. 2 will be explained.

As shown in FIG. 18, when the gradation signal S64 is reset by the load signal LOAD in the gradation control section 64, the gradation signal S64 becomes inactive state B (off state). Next, for example, when 4-bit data of "0" in hexadecimal notation is input to the gradation control section 64, the PJtA signal S64 remains off. When 4-bit data of '°1°' in hexadecimal notation is input, the load signal LOAD
The gradation signal S64 is turned on by the 14th pulse of the clock signal CPG counting from the clock signal CPG, and the gradation signal S64 having a pulse width that is turned off by the next load signal LOAD is output. When 4-bit data of "2'° is inputted in hexadecimal notation, 1
The gradation signal S64 is turned on by the third pulse of the tarock signal CPG, and turned OFF by the next load signal LOAD, and the gradation signal S64 is output. Similarly, 1
A gradation signal S64 of pulse width is obtained according to 4-bit data up to "F" in hexadecimal notation.

The gradation signal S64 from the gradation control section 64 obtained in this way is inputted to the 4-level driver 66 via the 80-bit level shifter 65, as in the above embodiment, and is converted into a data signal VS1 for driving the liquid crystal cell. ~vsso and output. These data signals VSI to VS80 are applied to the data electrodes 11-1, 11-2. TF via...
Applied to the source of T13. The timing of the scanning signal VG applied to the gate of the TPT 13 and the data signal VS is shown in FIG.

As shown in FIG. 19, the pulse width modulation driver 60 is
The time when the scanning signal VG is turned off is made to coincide with the time when the data signal VS is turned off.

For example, if the pulse width of the scanning signal VG is t2 and the data signal V
When the pulse width of S is tl, the data signal S is set to turn on at a time (t2-tlH&) after the scanning signal VG turns on.At such timing, the scanning signal VG turns on. In this state, no charge is accumulated in the liquid crystal cell 14 during the period (t2-tl) in which the data signal VS is in the off state.

When the scanning signal VG is turned on and the data signal VS is turned on, charge begins to accumulate in the liquid crystal cell 14.

The amount of charge accumulated increases with time.

Thereafter, when the scanning signal VG is turned off, the TFT 13 becomes non-conductive, the charges accumulated up to that point are held, and the voltage V1 corresponding to the amount of charge continues to be applied to the liquid crystal cell 14. Similarly, when the pulse width of the data signal ■s is t2, a voltage ■2 corresponding to the pulse width is applied to the liquid crystal cell 14.

The relationship between the pulse width and the transmittance of the liquid crystal is as shown in FIG. Therefore, similarly to the above embodiment, by determining the pulse width from the characteristics shown in FIG. 20, that is, in FIG. 18, the pulse setting of the clock signal CPG can be adjusted to match the characteristics shown in FIG. Data can be written in the memory 53 so that the video signal and the transmittance of the liquid crystal cell 4 are in a proportional relationship, thereby making it possible to obtain a gradation display with excellent reproducibility.

Note that the present invention is not limited to the illustrated embodiment; for example, the active element of the liquid crystal panel 10 may be replaced with another transistor or a bidirectional diode, etc., and the pulse width modulation driver 60 or the like may be replaced accordingly. Various modifications are possible, such as modifying the circuit such as the Y driver 21 to other circuit configurations.

(Effects of the Invention) As described in detail above, according to the first invention, when an active element is in an on state and a data signal applied thereto is in an inactive state, an electric charge is charged in a liquid crystal cell. Utilizing the characteristic of discharging with a certain time constant, we controlled the level of the data signal applied to the liquid crystal cell using a pulse width modulation driver to display gradations.
The following effects can be obtained.

(a) Excellent gradation display reproducibility that is not affected by the electro-optical characteristics of the liquid crystal cell can be obtained.

(b) The pulse width modulation driver has a latch function and can shift data simultaneously during the data signal output period, so it can be driven at a low drive frequency and the amount of power dissipated can be reduced.

According to the second invention, the voltage level of the data signal applied to the liquid crystal cell is applied to the liquid crystal cell by the pulse width modulation driver by utilizing the time required from the time when the active element becomes conductive until the voltage level of the data signal applied to the liquid crystal cell is saturated. Since the gradation display is performed by controlling the level of the data signal, the above (a>
, (b) can be obtained.

In the third and fourth inventions, desired gradation characteristics with excellent reproducibility can be obtained by setting data in the memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a gradation display drive circuit showing an embodiment of the present invention, FIG. 2 is a basic configuration diagram of a conventional active matrix liquid crystal display device, and FIG. 3 is a timing diagram of FIG. 4 is a configuration block diagram of a conventional video signal processing circuit, FIG. 5, FIG. 9, FIG. 16, FIG. 17, and FIG. 20 are electro-optical characteristic diagrams of liquid crystal, and FIG. The configuration diagram of the X driver shown in the figure, Figure 7 is the operation waveform diagram of Figure 6,
8(a), Cb) are operational waveform diagrams in FIG. 2, FIG. 10 is a block diagram of the A/D converter in FIG. 2, and FIG. 11 is a block diagram of the clock generation circuit in FIG. Figure 12 is a timing chart of the scanning signal and data signal of this embodiment, Figure 3 is an operation waveform diagram of Figure 1, and Figure 14 is the timing chart of the
cy) gradation time chart, FIG. 15 is a timing chart of the scanning signal and data signal of the embodiment of the present invention, FIG. 18 is another gradation time chart of FIG. FIG. 3 is a timing diagram of a scanning signal and a data signal in an embodiment. 10...Liquid crystal panel, 11-1 to 11-4...Data electrode, 12-1 to 12-4...Scanning electrode, 13...
・TFT, 14...Liquid crystal cell, 20...X driver, 21...Y driver, 40...A/D conversion section, 4
3-143-2...A/D conversion circuit, 50...Clock generation circuit, 53...Memory, 60...Pulse width modulation driver, 61.62...Shift register, 63
...Latch circuit, 64...Gradation control section, 65...
Level shifter, 66...driver. 10: Liquid crystal panel 11-1 to 11-4: Data electrode 12-1 to 12-4: Scanning electrode 13: TFr 14: Liquid crystal cell Conventional active matrix liquid crystal display device (■) Applied voltage liquid crystal electro-optics Characteristics Figure 5, Figure 6c! 1. Operating waveform diagram of FIG. 7. Relative video signal voltage 100. Electro-optical characteristics of liquid crystal. FIG. 9 (b). Operating waveform diagram of FIG. 2. Timing chart of signals and data signals Fig. 12 Fig. 11 Operation waveform chart OAD Fig. 11 Gradation time chart Fig. 14 Timing of scanning signals and data signals of the embodiment Fig. 15

Claims (1)

[Claims] 1. For a liquid crystal panel in which active elements and liquid crystal cells connected to orthogonal locations of scan electrodes and data electrodes are arranged in a matrix, a scan signal is supplied to the scan electrodes, and the In the gradation display drive circuit of an active matrix liquid crystal display device, which supplies a data signal with a predetermined pulse width to the data electrode to drive the gradation display of the liquid crystal panel, an analog video signal is converted into a digital video signal and output. an analog/digital conversion circuit that shifts and latches the digital video signal, performs pulse width modulation based on a gradation control clock signal, and converts the digital video signal into a pulse width having an activation period that matches the activation period of the scanning signal. A gradation display drive circuit for an active matrix liquid crystal display device, comprising: a pulse width modulation driver that generates a data signal and supplies the data signal to the data electrode. 2. In the gradation display drive circuit for an active matrix liquid crystal display device according to claim 1, the pulse width modulation driver shifts and latches the digital video signal, and performs pulse width modulation based on a gradation control clock signal. A gradation display drive circuit for an active matrix liquid crystal display device, wherein the gradation display drive circuit for an active matrix liquid crystal display device is configured to generate a data signal having a pulse width having an inactivation period that matches the inactivation period of the scanning signal and supply it to the data electrode. 3. The gradation display drive circuit for an active matrix liquid crystal display device according to claim 1 or 2, further comprising: a counter that performs a counting operation using a clock pulse of a constant period and outputs a plurality of frequency-divided pulses, and an output pulse of the counter. A gradation display drive circuit for an active matrix liquid crystal display device that generates a gradation control clock signal to be input to the pulse width modulation driver using a memory that outputs storage data at a specified address. 4. In the gradation display drive circuit for an active matrix liquid crystal display device according to claim 3, the gradation control clock for each gradation level is set such that the transmittance of the liquid crystal cell and the video signal are approximately proportional to each other. A gradation display drive circuit for an active matrix liquid crystal display device, wherein data in which a pulse width of a signal is set is stored in the memory in advance.