JPH0362685A - Scanning converter for video signal - Google Patents

Abstract

PURPOSE:To obtain an excellent high vision signal without deterioration in picture quality, causing a problem of defective interlace due to field mis- discrimination and a border problem by interleaving a scanning line of an input video signal to obtain a noninterlace signal. CONSTITUTION:An input video signal SVS is supplied to an A/D converter 4 and fed to an interleave circuit 5. Then band limit of a spatial frequency is implemented by an LPF limiting band of a vertical spatial frequency compo nent and the the scanning line is interleaved. How the scanning line is to be interleaved is controlled based on number of scanning lines of one frame of the signal SVS. The output signal of the circuit 5 is converted into a noninterlace signal in which number of scanning lines of one field is nearly 1/2n or 1/3n of the umber of scanning lines of one frame of the signal SVS and the signal is written in a frame memory 7. Then a video signal for High Vision pattern is read while being subject to interlace conversion from the memory 7.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a scanning line number conversion device that converts an interlaced television signal to a non-interlaced signal, a down converter device applying the same, and a down converter device incorporating the same. This relates to a two-screen television receiver.

[Prior Art] A scanning line number conversion device that appropriately processes an interlaced input television signal to obtain an output television signal with a different number of scanning lines from that of the input is generally included in various devices that embody the purpose. handled in the form. Devices that embody this purpose include, for example, 2i single-screen television receivers (for example, Nikkei Electronics April 14, 1980 issue, Japanese Patent Publication No. 59-37913, Japanese Patent Application Laid-open No. 62
-Refer to Publication No. 269482 etc.>, Hi-Vision/N
TSC down converter device, (for example, patent application No. 1-
See No. 120128).

All of these devices include a scan line number conversion device. Such a scanning line number conversion device is configured depending on the purpose of use of the included device, but it is generally configured so that the number of scanning lines of the output signal is smaller than the number of scanning lines of the input signal. It is.

First, the conventional technology regarding such a scanning line number conversion device will be explained.

A scan line can generally be interpreted as a vertical sample of a two-dimensional sample of a television screen. Therefore, reducing the number of scan lines is equivalent to reducing the vertical sampling frequency of the television screen. Such an operation can be realized by the action of two components:

In other words, the vertical spatial frequency component of the television screen is
They are a band-limiting filter that limits the vertical sampling frequency to 1/2 or less of the reduced vertical sampling frequency, and a scanning line thinning circuit that thins out the scanning lines to reduce the vertical sampling frequency of the television screen. This operation completely follows the sampling theorem, and the principle of operation is self-evident.

By the way, FIG. 2A shows each field f1. of the interlaced signal. f2. . . . shows the scanning line position for each. In the figure, the "0" mark represents a scanning line, and its position is shifted by one line in the vertical direction for each field. Further, FIG. 2B shows the scanning line position for each field of the non-interlaced signal. In the same figure, the "O" mark and "x" mark represent scanning lines.
The "O" mark is a scanning line corresponding to the interlaced signal, and the "x" mark is a scanning line created as appropriate by interpolating from the interlaced signal, and the scanning line exists at the same position in all fields.

In FIG. 2, the horizontal axis indicates the time direction in units of field periods, and the vertical axis indicates the vertical direction in units of scanning line intervals.

FIG. 3A shows the basic configuration of an apparatus that inputs such an interlaced signal and converts the number of scanning lines.

The signal applied to the input terminal 500 is band-limited by a vertical spatial frequency limiting low-pass filter f)01, and then guided to the decimation circuit 502.
As shown in Figure B, scanning lines are thinned out and
A scanning line signal corresponding to the xj mark is output from the output terminal 503.

In Figure B, the "○" marks are scanning lines corresponding to input signals, and the "x" marks are scanning lines corresponding to output signals. Further, 0 represents the tap range of the vertical spatial frequency limiting low-pass filter.

Now, the television signal input to such a scanning line number converter V& is an interlaced signal. Therefore, the output signal with the reduced number of scan lines shown in FIG. 3B is also interlaced.

Incidentally, in a device including a scanning line number converter that outputs such a signal, the signal is further processed depending on the purpose of use.

In this case, since the signals handled are interlaced,
It is often necessary to determine the interlaced ranking using a field determining means. In other words, in conventional technology, field determination is performed on interlaced signals in this way, and subsequent signal processing is performed based on the result. has been done.

Below, we will discuss the two examples listed above and explain why field determination is necessary for signal processing.

First, a two-screen television will be explained as an example.

The basic configuration of a two-screen TV is 8 light electronics 1
It is described in the April 14, 1980 issue.

That is, an image memory is provided to absorb the time difference between the video signal for the main screen and the video signal for the sub-screen, and the video signal for the sub-screen is written to the image memory according to the synchronization, and the video signal for the main screen is written to the image memory according to the synchronization. The sub screen is configured to be displayed at a predetermined position of the main screen by reading out the video signal in synchronization with the video signal.

There are two technical problems with a dual-screen television having such a configuration. In the prior art, field determination means are used to solve these problems.

All of these problems occur because the signal phases of the video signal for the main screen and the video signal for the child screen do not match with each other.

First, if the interlace relationship between the video signal for the main screen and the video signal for the child screen does not match, the above-mentioned image memory is generally processed field by field, so There is a problem that the interlacing of the child screen is reversed (a problem of insufficient interlacing).

When the interlace relationship is reversed in this way, severe line flicker, double image disturbance, etc. occur on the child screen.

Second, if the vertical synchronization signal phases of the video signal for the main screen and the video signal for the child screen do not satisfy a certain relationship,
The problem is that while reading the video signal for the sub-screen from the image memory mentioned above, its contents are rewritten to the next field information, resulting in images of different fields being displayed above and below the sub-screen (Boundary B) There is.

When images of different fields are displayed above and below the sub-screen in this way, the scanning lines on the border lines are clearly observed, especially in the case of moving images, resulting in an unsightly hindrance. Further, since the interlace relationship is reversed above and below the boundary line, not only the scanning lines on the boundary line are observed, but also the first problem mentioned above occurs at the same time. In other words, a normal image is obtained only on either the upper or lower side of the boundary line, and line flicker, double image disturbance, etc. occur on the other side.

These two problems are fundamental problems that must be solved in order to improve the image quality of dual-screen televisions, and solutions using field determination means have been proposed in the past.

First, for the first problem, determine the fields of both the main screen video signal and the child screen video signal, and based on the field determination result of the child screen video signal,
The video signal for the child screen is written in a predetermined area of the image memory, and on the other hand, the video signal for the child screen is read out from an appropriate starting phase based on the field determination result of the video signal for the main screen, thereby: It has been proposed to match the interlace relationship between the video signal for the main screen and the video signal for the child screen (Japanese Patent Publication No. 59-37913 #T
IM).

Next, for the second problem, divide the image memory into four areas, allocate two areas each for the first and second fields, and prevent overtaking by controlling to prevent reading and writing in the same area at the same time. It has been proposed to provide a circuit to prevent so-called overtaking, in which the contents of the video signal for the sub-screen are rewritten to the next field information while the video signal for the sub-screen is being read from the image memory (Japanese Patent Application Laid-Open No. (See Publication No. 62-269482).

That is, based on the field determination result of the video signal for the sub-screen, the video signal for the sub-screen is written into a predetermined area of the image memory.On the other hand, the overtaking prevention circuit writes the field of the video signal for the main screen. Of the two areas in which field information matching the judgment result is written, the video signal for the child screen is read from the one written first.

As a result, each area of the image memory has a first-in memory.
Reading and writing are performed first out, and reading always precedes reading and writing of field information, so overtaking can be prevented as described above.

As described above, the first and second problems are individually solved using field determination means.

Also, if a control function is added to the overtaking prevention circuit in the solution method for the second problem to match the interlace relationship between the video signal for the main screen and the video signal for the child screen shown in the solution method for the first problem. , two problems can be solved at the same time.

As described above, the field determination means is indispensable for the two-screen television technology.

Next, a high-definition/NTSC down converter device will be explained as an example.

This device can handle interlaced high-definition signals with a field rate of 60.0 Hz and 1125 scanning lines per frame, and interlaced television signals with a field rate of 59.94 Hz and 525 scanning lines per frame. This is a device that converts

Therefore, this device has two points.

These are frame rate conversion and scanning line number conversion.

Of these, the problems associated with frame rate conversion are
This problem is thought to be the same as the problem associated with phase alignment between parent and child, which was explained in the section on screen television. In other words, boundary problems are expected to occur due to overtaking.

However, this problem can be solved by applying the field determination method using the method described in Japanese Patent Laid-Open No. 62-269482.

However, many of the downconverters currently available do not perform frame rate conversion, and although it has been pointed out that boundary problems will occur if frame rate conversion is performed in the future, there is no way to resolve this. The current situation is that no problems have arisen.

On the other hand, regarding scanning line number conversion, the previous patent application No. 1-120
This is specified in issues such as No. 128.

The device will be explained below. The device responds to the input signal by
a field determining means for determining whether the current field is an even field or an odd field; a scanning line number converting means for setting the number of scanning lines of the odd field and the even field of the interlaced video signal to 525, respectively; A positioning means is provided for adjusting the position of one of the odd field and even field scanning line signals outputted from the means to the position of the other, and the input signal is converted into a non-interlaced television signal of 525 lines per frame. act.

Since the signal output from the scanning line number conversion means is an interlaced signal, the scanning line position differs for each field. For this reason, this device is configured to adjust the scanning line position of one of the fields to the other based on the result of field determination, thereby preventing line flicker from occurring.

Here, the field determination means is, for the device,
It is one of the essential elements to prevent line flicker from occurring.

As described above for the two examples, in the prior art, in a device including a scanning line number conversion device, field determination means is used as an essential means for achieving the purpose.

[Problem to be Solved by the Invention] By the way, if the field determination means is configured as described above and operates correctly, it will operate without problems with the scanning line number converter and the device including them, and it is possible to Problems can also be prevented.

However, the device may not operate properly, for example when using a reproduced video signal from a home VTR.

The reason for this is that the field determining means used in the problem solving method may malfunction with respect to the reproduced video signal of the home VTR.

The reason why the field determination means malfunctions with respect to the reproduced video signal of a home VTR is that noise caused by head switching is mixed in the vicinity of the vertical synchronization signal. Since the field determination means generally determines the field order by comparing the phases of the horizontal synchronization signal and the vertical synchronization signal, as mentioned above, if noise enters the vicinity of the vertical synchronization signal, the field determination operation may be incorrect. be.

Such malfunctions occur with a high probability during special playback such as picture search and slow playback.

Furthermore, such malfunctions occur not only with respect to the full video signal of a home VTR, but also with video signals from a still image photo player or a television game machine. The reason why malfunctions occur with respect to video signals from these devices is not due to noise as described above, but because the output video signals themselves are not originally interlaced.

The operation of the field determination means for non-interlaced video signals is generally not defined at all.For example, it continues to output a determination output for either the first or second field, or it continues to output a determination output for either the first or second field. The output is erratic or completely undefined. When using the above-described first and second problem solving methods for such an output, there are cases where the problem is solved effectively and cases where it is not solved with equal probability. In other words, problem solving may not be effective.

When malfunctions of the field determination means are taken into consideration, there are limits to signal processing that relies on the field determination means as described above.

The above can be summarized as follows. That is, the field determination means is a conventional scanning line number converter,
And in devices that include it, it is used as an indispensable and essential means for achieving its intended purpose. However, the field determining means may malfunction, and such erroneous determination may impede the overall purpose of use of the apparatus including the scanning line number converter. These can occur, for example, in the form of line flicker.

Such a problem can be avoided if the output signal of the scanning line number conversion device can be made into a non-interlaced signal.

This is because a non-interlaced signal originally does not have the concept of field, and therefore there is no need to introduce field determination means even in a device including a scanning line number converter.

Therefore, in the present invention, firstly, a scanning line number conversion device is constructed which can obtain a non-interlaced output signal without using a field determining means.

Second, a down converter device that does not require the use of field determination means is configured as an AT device that includes the same scanning LA number conversion device.

Regarding dual-screen TV receivers with a built-in down converter device, there has been no corresponding concept in the past.
If we dared to realize this receiver, we would need a down converter device and a two-screen TV signal processing circuit (see the above document).
), and will be able to switch between them depending on the purpose. However, such a configuration has the problem of an unavoidable increase in cost because it has 2M built-in signal processing circuits that cannot be shared.

[f! Means for Solving the Problem] To solve the above problem, a scanning line number conversion device according to a first invention includes a low-pass filter that band-limits the vertical spatial frequency component of an input video signal, and a scanning line thinning device. The image forming apparatus includes a jump circuit and a thinning control circuit that controls the thinning circuit based on the number of scanning lines in one frame of an input video signal.

Further, the down converter device according to the second invention is provided with the first down converter device.
A scanning line number converter according to the invention, a frame memory in which writing and reading of signals are performed and the writing and reading can be controlled asynchronously; and write control means for controlling not to write to the field portion.

Further, the two-screen television receiver with a built-in down converter device according to the third invention uses the scanning line number conversion device according to the first invention to write and read signals, and to perform the writing and reading asynchronously. A frame memory that can be controlled, a write control means that controls not to write to the field portion until reading of signals for one field from the frame memory is completed, a clock frequency, a write range of the frame memory,
The device is equipped with a function switching unit that controls the readout range, and is configured to be able to switch between the down converter function and the two-screen TV function according to the user's needs.

[Function] In the scanning line number conversion device according to the first invention, regardless of whether the input video signal is interlaced or not, and regardless of the number of scanning lines per frame, the input video signal is always non-interlaced. It is converted into a signal and output. At this time,
The input video signal is band-limited in spatial frequency by a low-pass filter that band-limits vertical spatial frequency components, and then the scanning lines are thinned out. How the scanning lines are thinned out is controlled based on the number of scanning lines in one frame of the input video signal.

The output signal is converted into a non-interlaced signal in which the number of scanning lines in one field is approximately 1/2n or approximately 1/3n (where n is a natural number) of the number of scanning lines in one frame of the input video signal. .

In this way, since a non-interlace signal is output, there is no need for field determination means for the output video signal in subsequent operations.

Furthermore, the down converter device according to the second aspect of the invention that includes such a scanning line number conversion device can handle non-interlace converted signals. therefore,
There is no need to use field determination means, and problems associated with malfunctions of the field determination means can be avoided.

In addition, the non-interlace converted signal is written to the frame memory, and writing to that field part is not performed until reading of one field from the same frame memory is completed, and if it becomes necessary, it is written to another field part. By doing this, while the video signal is being read from the frame memory, its contents are rewritten to the next field information, resulting in a boundary problem (on dual-screen TVs) where images of different fields are displayed at the top and bottom of the screen. The phenomenon described in the section of the prior art does not occur.

In other words, since the signal written to the frame memory is always controlled to be non-interlaced, it is not necessary to match the write field of the frame memory and the field of the input video signal.
It becomes possible to perform an operation of switching the write field by considering only the boundary problem.

Moreover, by doing so, each read and write of the frame memory operates asynchronously.

Therefore, frame rate conversion can also be realized without requiring any new additional circuitry.

Finally, the second invention with a built-in down converter device according to the third invention.
In addition to the functions of the down converter device according to the second aspect of the invention, the screen television receiver operates to control the clock frequency, frame memory writing and reading range according to the purpose. This makes it possible to share the circuit related to the down converter function with the circuit related to the two-screen television function.

[Embodiment] Hereinafter, an embodiment of a scanning line number conversion device and a down converter device will be described with reference to FIG.

Furthermore, a two-screen television receiver with a built-in down converter device will be explained last.

In FIG. 1, an input terminal 1 is supplied with a reference video tl signal SVs, for example, an NTSC signal.

This video signal Sv■ is connected to a fixed terminal m of the changeover switch 2.

As described later, the video signal SVm is synchronously separated and used as a timing reference for outputting a signal from the down converter device, so any video signal may be used.

Further, the input terminal 3 is supplied with a video signal SVs, for example, a high definition signal. This video signal sVS is converted into a digital signal by the A/D converter 4, and then is thinned out v! I
5. The operation of this thinning circuit 5 is controlled by a thinning control circuit 6.

The output signal of the thinning circuit 5 is then supplied as a write signal to a frame memory 7 composed of, for example, a RAM. The write operation in this frame memory 7 is as follows:
It is controlled by the write control circuit 8.

Further, the video signal SVs supplied to the input terminal 3 is supplied to the synchronization separation circuit #J9, and the vertical interval 1t118 WVD and horizontal synchronization signal WHD separated by this separation circuit 9 are sent to the thinning control circuit N6 and the write 111m circuit 8. supplied to

Further, 10 is a write clock generation circuit composed of, for example, a PLL circuit, and a clock WCK outputted from this generation circuit 10 is supplied to an A/D conversion W4, a thinning circuit 5, and a thinning control circuit 6.

The above-described thinning circuit 5 reduces the vertical sampling frequency. In this case, scanning lines are thinned out in the vertical direction. Note that when reducing the sampling frequency, a low-pass filter corresponding to the reduced frequency is inserted in advance so that signal components higher than the Nyquist frequency do not exist.

In addition to the sampling frequency reduction process described above, the thinning circuit 5 performs a process of forming a non-interlaced signal by interpolating the scanning line signal.

Here, the sampling frequency reduction process and the non-interlaced signal formation process will be described in detail.

Here, the number of scanning lines in one field of the output signal is 1/2 of the number of scanning wA in one frame of the input signal, l/3.1/4
This will be explained using an example.

If these are used in combination, almost any number of scanning lines can be realized.

Also, here, the key points are the vertical sampling frequency reduction process and the process of forming a non-interlaced signal without using a field determination means. Therefore, the explanation will focus on these two points.

First, a case will be described in which the number of scanning lines in one field of the output signal is set to 1/2 the number of scanning lines in one frame of the input video signal.

For convenience, the number of lines in one field of the video signal SVs is 9.
If it is 0, 1 of the non-interlaced signal to be output
The number of lines in the field is Qn ÷ 2 This means that it will double.

In this way, the number of lines in one field to be output is equal to the number of lines in one field of the video signal SVs, so non-interlacing is performed as follows.

When the number of lines in one frame of the video signal SVs is an even number, it is considered that the video signal SVs itself is a non-interlaced signal, so the scanning line signal of any field of the video signal SVs is directly transferred to each of the non-interlaced signals. Assigned to field scanning line signals.

The number of lines in one frame of the video signal SVs is 2.
When there are n+1 pulses (n is a positive integer) and an odd number, the following processing is performed in each frame period based on the frame pulse obtained by dividing the vertical synchronizing signal WVD by 1/2.

That is, the first n scanning line signals of the video signal SVs are directly assigned to the scanning line signals of one field of the non-interlaced signal. Subsequently, the remaining n+1 scanning line signals of the video signal SVs are used to form an interpolated scanning line signal such that the scanning line exists at the same position as the above n scanning lines, and this interpolated scanning line signal is assigned to the scanning line signal of the other field of the non-interlaced signal.

FIG. 4A shows the video signal SVs, and the "O" marks are scanning lines. Also, B in the same figure shows a non-interlaced signal written into the frame memory 7, and the "x" mark is a scanning line based on an interpolated scanning line signal.

The interpolated scanning line signal is formed, for example, by arithmetic averaging processing of the upper and lower lines. In other words, in the remaining n+1 lines based on the frame pulse, two scanning lines are combined as shown by the solid line in FIG.
2, thereby forming an interpolated scan line signal.

FIG. 5B shows a non-interlaced signal formed as described above. In this case, by arranging the vertical positions of each scanning line as shown in FIG. 3A, it is easy to understand which position each scanning line corresponds to in the video signal SVs.

In other words, the 21st scanning line of the non-interlaced signal is at the 91st position of the video signal SVs, the Q2 scanning line of the non-interlaced signal is at the 93rd position of the video signal SVs, and so on. to form a non-interlaced signal.

By the way, as mentioned above, the frame pulse is used as a reference, but when the phase of the frame pulse is reversed, an interpolation scanning line signal is formed as shown in FIG. 6A, and as shown in FIG. 6B. Thus, a non-interlaced signal is formed. In this case, Ql of the non-interlaced signal
The scanning line corresponds to the position 92 of the video signal SVs, the scanning line Q2 of the non-interlaced signal corresponds to the position Q4 of the video signal SVs, and so on. However, the scanning line position for each field is constant, and a non-interlaced signal is similarly formed.

In FIGS. 4 to 6, the number of lines in one frame of the video signal SVs is 11. However, in the case of an odd number of lines, a non-interlaced signal is generally formed in the same manner.

FIG. 7 shows an example of a specific configuration of the thinning circuit 5 and the thinning control circuit 6 for performing the above-described processing.

In the figure, the video signal SVs from the A/D converter 4 is supplied to the am fixed terminal of the changeover switch 51v. Further, this video signal SVs is directly supplied to the adder 52v, and is also supplied to the adder 52v via a line memory 53v that constitutes a delay element having a delay time of l horizontal period. In the adder 52v, the two signals are each 1/2
The output signal is supplied to the bw fixed terminal of the changeover switch 51v as an interpolated scanning line signal.

Further, the vertical synchronization signal WvD from the synchronization separation circuit 9 is supplied to a frame order circuit 61 comprised of, for example, a T flip-flop, a gate circuit, and the like.

This frame order circuit 61 divides the vertical synchronizing signal WVD into 1/2 to form a frame pulse WFP, and also forms a signal SFP indicating whether the field includes this frame pulse WFP.

The frame pulse WFP from the frame order circuit 61 is
For example, a line number counting circuit 6 configured using a counter
At the same time, the horizontal synchronization signal WHD from the synchronization separation circuit 9 is also supplied to the counting circuit 62, and the number of lines in one frame is counted. And this counting circuit 6
The line number data of one frame from No. 2 is supplied to the status determination circuit 63, and it is determined whether the number of lines of one frame is even or odd.

Also, the frame pulse WFP from the frame order circuit 61
is supplied to a line timing display circuit 64 composed of, for example, a counter, and the horizontal synchronization signal WHD from the synchronization separation circuit 9b) is supplied to this timing display circuit 64.
is supplied. The timing display circuit 64 counts the number of the current line counting from the frame pulse WFP.

The signal SFP from the frame order circuit 61, the determination signal from the status determination circuit 63, and the count data from the timing display circuit 64 described above are supplied to the changeover switch 51v of the thinning circuit 5 as a switching control signal.

That is, when the number of lines in the l frame is an even number, the changeover switch 51v remains connected to a(11).On the other hand, when the number of lines in the l frame is odd, the changeover switch 51v is connected to a(11) from the frame pulse to the n line. The period is all
and bm for the remaining n+1 line period.

As a result, the number of scanning lines is 1 from the changeover switch 51v.
/2 non-interlaced signal is output.

In addition, in the thinning control circuit 6, the frame order circuit 6
The signal SFP from 1, the determination signal from status determination circuit 63, and the count data from timing display circuit 64 are supplied to line address control circuit 65. The line address control circuit 65 sends a line address increment signal TNC to the write control circuit 8.
is supplied. In addition, this increment 1 word INC
is also supplied as an output enable signal WE, as will be described later.

Next, a case where the number of scanning lines is 1/3 will be explained.

For convenience, the number of lines in one field of the video signal SVs is 9.
If it is 0 lines, the number of lines in one field of the non-interlaced signal to be output is Qn÷3X2=29n
/3 C books]. Here, "÷3" indicates that the number of scanning lines is 1/3, and "x2" indicates that the number of scanning lines is doubled due to non-interlacing.

In this way, the number of lines in the l field to be output is 273, which is the number of lines in one field of the video signal SVs, so non-interlacing is performed as follows according to the number of lines in one frame of the video signal SVs. be done.

When the number of lines in one frame of the video signal SVs is an even number (for example, 526, 626, 1050, 1250, etc.), the video signal SVs itself is considered to be a non-interlaced signal.In this case, the video signal SVs itself is considered to be a non-interlaced signal. For each field of the signal SVs, 3n+0, 3n+1 .
3n Two scanning line signals are formed from the 2nd scanning line signal, and these are assigned to the scanning line signals of each field of the non-interlaced signal.0For example, the following control is repeated every 3 lines to form the be done.

In the 3n+0th line, the current scanning line signal and the scanning line signal l lines before are each added at a ratio of 1/2 to form a scanning line signal of a non-interlaced signal.

In the 30,001-th line, a scanning line signal of a non-interlaced signal is not formed.

In the 3nth, 2nd line, the current scanning line signal, the scanning line signal of l line before, and the scanning line signal of 2 lines before are as follows.
They are added at a ratio of 1/4, 1/2 and 1/4, respectively, to form a scanning line signal of a non-interlaced signal.

Also, the number of lines in one frame of the video signal SVs has increased to 6+
If there are 3 lines (k is a positive integer, for example 525 lines, 627 lines, 1125 lines, etc.), the vertical equivalent signal WV
Dti: Based on the frame pulse obtained by dividing the frequency by l/2, i! is calculated every 3 lines in each frame period. 1III
j is repeated to form a scanning line signal of a non-interlaced signal.

81st! IA indicates the video signal SVs, and “○J
The marks are scan lines. Also, same v! iB indicates a non-interlaced signal to be output, and the "x" mark is a scanning line. In this case, each scanning line signal of the non-interlaced signal is calculated and formed from a plurality of scanning line signals of the video signal SVs.

For example, the following control is repeated every three lines in each frame period.

That is, 3n+O (0°3.6.
...)-th line, the current scanning line signal shown surrounded by a broken line in FIG. A line signal is formed.

Further, in the 3n+1 (1, 4, 7, . . . ◆)-th line, a scanning line signal of a non-interlaced signal is not formed.

In addition, in the 3n+2 (2, 5, 8,...)th line, the current scanning line signal, the scanning line signal of one line before, and the scanning line of two lines before, which are shown surrounded by solid lines in FIG. The signals are summed at a rate of 1/4, 1/2 and 1-/4, respectively, to form a non-interlaced scan line signal.

In addition, in FIG. 9A, "■Cx=O~14)" is a scanning line.

Further, FIG. 9B shows a non-interlaced signal formed by repeating the above control, and the "X" marks are scanning lines. In this case, by aligning the vertical position of each scanning line with A in the same figure, the position of each scanning line can be adjusted to match the video signal SV.
s makes it easy to understand which position it corresponds to.

In other words, the 91st scanning line of the non-interlaced signal is processed to correspond to the Q2 position of the video signal SVs, the 22nd scanning line of the non-interlaced signal is located to the 123' position of the video signal SVs, and so on. A non-interlaced signal is formed.

By the way, as mentioned above, the frame pulse is used as a reference, but when the phase of the frame pulse is reversed, the process shown in FIG. 10A is performed, and as shown in FIG. 10B, the non-interlaced signal is It is formed. In this case, scanning line 21 of the non-interlaced signal is placed at position 91 of the video signal SVs, and scanning line 92 of the non-interlaced signal
The scanning line corresponds to the position 92' of the video signal SVs, and the same position thereafter, and is shifted by two lines compared to the example in FIG. 9, but the scanning line position for each field is A non-interlaced signal is formed as well.

In addition, although the number of scanning lines of the video signal SVs is explained as 15 in FIGS. 8 to 10, the same applies to cases where the number of scanning lines is generally 6 + 3, such as 525, 627, 1125, etc. A non-interlaced signal is formed.

Also, the number of lines in one frame of the video signal SVs has increased to 6+
If there is one line (k is a positive integer, for example, 523 lines, 625 lines, etc.), control is repeated every three lines to form a non-interlaced scanning line signal. In this case, the control is made to be different between a field in which a frame pulse obtained by dividing the vertical equal amount signal WVD by 1/2 exists and a field in which it does not exist.

FIG. 11A shows the video signal SVs, and the "O" marks are scanning lines. Also, Figure B shows the non-interlaced signal that is output, and the "x" marks are scanning lines. In this case, each scanning line signal of the non-interlaced signal is calculated and formed from a plurality of scanning line signals of the video signal SVs.

For example, in fields where frame pulses exist and fields where there are no frame pulses, the following control is repeated every three lines.

That is, in FIG. 12A, if there is a frame pulse in field fl, then in field f1 there are 3n+0 (0, 3, 6, . . . ) from the frame pulse.
)th line, the current scanning line signal shown surrounded by a solid line in FIG. (The words are added at the rate of 1/4, 1/2 and 1/4, respectively, to form a non-interlaced scan line signal.

Further, in the 3n+1 (1, 4, 7, . . . )th line, a scanning line signal of a non-interlaced signal is not formed.

Furthermore, in the 3n+2 (2, 5, 8, ·◆・)th line, the scanning line signal of the l line before and the scanning line signal of 2 lines before, which are shown surrounded by broken lines in FIG. 12A, are each 1/
The signals are added at a ratio of 2 to form a scanning line signal of a non-interlaced signal.

In addition, in field f2 where there is no frame pulse, 3n+0 (12° 15.1B,
...), the current scanning line signal and the scanning line signal from the previous line, which are shown surrounded by broken lines in FIG. A line signal is formed.

Also, 3n+1 (13,16,19,* ・
-)-th line, a scanning line signal of a non-interlaced signal is not formed.

Also, 3n+2 (11, 14, 17,... ◆
)th line, the current scanning line signal, the scanning line signal 1 line previous, and the scanning line signal 2 lines previous, shown surrounded by solid lines in FIG. 12A, are l/4.1/2 and 1 line, respectively. The signals are added at a ratio of /4 to form a scanning line signal of a non-interlaced signal.

In addition, in Fig. 12A, “■(x == 0 to 1
8)" is a scanning line.

Further, FIG. 12B shows a non-interlaced signal formed by repeating the above control, and the "x" marks are scanning lines. In this case, by aligning the vertical position of each scanning line with A in the same figure, the position of each scanning line can be adjusted to the video signal S.
Vs makes it easy to understand which position it corresponds to.

In other words, the 91st scanning line of the non-interlaced signal is processed to correspond to the 91' position of the video signal SVs, the 92nd scanning line of the non-interlaced signal is located to the Q3 position of the video signal SVs, and so on. A non-interlaced signal is formed.

In the above explanation, the scanning line signal of the non-interlaced signal is not formed in the 3n+1st line of the field where the frame pulse exists, and the scanning line signal of the previous line and the scanning line signal of the 2nd line before is formed in the 3n+2nd line. Although a scanning line signal of a non-interlaced signal is formed from a scanning line signal, this may be done as follows.
That is, on the 3n+1st line, a non-interlaced scanning line signal is formed from the current scanning line signal and the previous scanning line signal, and on the 3n+2nd line, a non-interlaced scanning line signal is not formed. You can also do this.

By the way, if the phase of the frame pulse is reversed,
The processing shown in FIG. 13A is performed, and a non-interlaced signal is formed as shown in FIG. 13B. In this case, the 91 scanning lines of the non-interlaced signal are the video signal SV
The scanning line 92 of the non-interlaced signal corresponds to the position 93' of the video signal SVs, and the same position below, and the scanning line 92 of the non-interlaced signal corresponds to the position 92 of Although the scanning line position is shifted by a minute, the scanning line position for each field is constant, and a non-interlaced signal is similarly formed.

Note that in FIGS. 11 to 13, the number of scanning lines of the video signal SVs is 19, but for example, 523, 625
In general, when the number of scanning lines is 6+1, such as in a book, a non-interlaced signal is formed in the same way.

Also, the number of lines in one frame of the video signal SVS has increased to 6+
When there are five lines (k is a positive integer, for example, 527 lines, 623 lines, etc.), control is repeated every three lines to form a non-interlaced scanning line signal. As in the case where the number of lines in one frame is 6 + 1,
The control is made to be different between a field in which a frame pulse obtained by dividing the vertical synchronization signal WVDlt by 1/2 exists and a field in which it does not exist.

FIG. 14A shows the video signal SvS, and the "○" marks are scanning lines. Also, Figure B shows the non-interlaced signal that is output, and the "x" marks are scanning lines. In this case, each scanning line signal of the non-interlaced signal is calculated and formed from a plurality of scanning line signals of the video signal SvS.

For example, in fields where frame pulses exist and fields where there are no frame pulses, the following control is repeated every three lines.

That is, in FIG. 15A, if there is a frame pulse in field f1, in this field f1, 3n+0 (0, 3, 6, . . .
)th line, the current scanning line signal and the scanning line signal from the previous l line, which are shown surrounded by solid lines in FIG. It is formed.

Also, a n + 1 (1,4* 7+ ◆◆・
)-th line, a scanning line signal of a non-interlaced signal is not formed.

Furthermore, in the 3n+2 (215, 8,...)th line, the current scanning line signal, the scanning line signal of one line before, and the scanning line signal of two lines before are shown surrounded by broken lines in FIG. 15A. , are added at a ratio of 1/4, 1/2 and 1/4, respectively, to form a scanning line signal of a non-interlaced signal.

In addition, in field f2 where there is no frame pulse, 3n+O(9, 12, 15, . . .
・)th line, the current scanning line signal, the scanning line signal of the previous l line, and the 2nd scanning line signal shown surrounded by broken lines in FIG.
The scanning line signals of the previous line are added at a ratio of 1/4, 1/2 and 1/4, respectively, to form a scanning line signal of a non-interlaced signal.

Further, in the 3n+1 (10, 13, 16, --.)th line, a scanning line signal of a non-interlaced signal is not formed.

Also, in the 3n+2 (If, 14....)th line, the 151st! The scanning line signal of one line before and the scanning line signal of two lines before are shown surrounded by solid lines in IA.
They are each added at a rate of 1/2 to form a scanning line signal of a non-interlaced signal.

In addition, in Figure 15A, "■ (x = 0 to 16)"
is a scan line.

Further, FIG. 15B shows a non-interlaced signal formed by repeating the above control, and the "X" marks are scanning lines. In this case, by aligning the vertical position of each scanning line with A in the same figure, the position of each scanning line can be adjusted to the video signal S.
vS makes it easy to understand which position it corresponds to.

In other words, the scanning line 91 of the non-interlaced signal is processed to correspond to the position 92 of the video signal SvS, the scanning line 92 of the non-interlaced signal is located to the position 93' of the video signal SVS, and so on. A non-interlaced signal is formed.

In the above explanation, the scanning line signal of the non-interlaced signal is not formed in the 3n+1st line of the field where no frame pulse exists, and the scanning line signal of the previous l line and the 2nd line are not formed in the 3n102nd line. A scanning line signal that is a non-interlaced signal is formed from the previous scanning line signal, but this may be done as follows.In other words, at the 3n+1@th line, the current scanning line signal and the l line before the current scanning line signal are formed. A scanning line signal of a non-interlaced signal may be formed from the scanning line signal of , and a scan & I flaw signal of a non-interlaced signal may not be formed in the 3n+2th line.

By the way, if the phase of the frame pulse is reversed,
The processing shown in FIG. 16A is performed, and a non-interlaced signal is formed as shown in FIG. 16B. In this case, the 21 scanning lines of the non-interlaced signal are the video signal SvS
At position 92' of the non-interlaced signal! The scanning line g2 now corresponds to the Q4 position of the video signal SVS, and the same positions thereafter, and is 1
Although shifted by a line, the scanning line position for each field is constant, and a non-interlaced signal is similarly formed.

Note that in FIGS. 14 to 16, the number of scanning lines of the video signal SvS is 17, but for example, 527, 623
In general, when the number of scanning lines is 6 + 5, such as in a book, a non-interlaced signal is formed in the same way.

FIG. 17 shows a specific example of the structure of the thinning circuit 5 and the thinning control circuit 6 for performing processing when the number of scanning lines is set to 173 as described above.

In the figure, video No. 18 SVs from A/D converter 4
is supplied to a series circuit of line memories 54v and 55v forming an M extension element having a delay time of one horizontal period. The output signals of the line memories 54V and 55v are then supplied to an adder 56v, where they are each added at a rate of 1/2, and then supplied to the CL fixed terminal of the changeover switch 57v. In addition, the video signal SV on the A/D conversion side 4
s, the output signal of the line memory 54v and the output signal of the line memory 55v are supplied to the addition B 58v, and are added at the ratio of 1/4.1/2 and 1/4, respectively. Supplied to fixed terminals. Further, the video signal SVs of the A/D conversion side 4 and the output signal of the line memory 54v are supplied to an adder 59v, where they are each added at a ratio of 1/2, and then the ag! 1 fixed terminal.

In addition, in the status determination circuit 63 of the thinning control circuit 6, the number of scanning lines is even, 6+1, 6+3, and 6.
It is determined which one of the +5 lines corresponds to the above. That is,
It is determined whether the number of lines is an even number based on the line number data for one frame from the line number counting circuit 62, and if it is an odd number, the remainder when divided by six is determined. This status determination circuit 63 can be configured with hardware, but the RO
It can be easily configured using M.

The capacity of the ROM used here is normally 52 scanning lines.
If there are about 5 lines, the number of bits will be 2 as shown below. That is, if line number data is supplied to the ROM address, 10 bits are required. Also, since there are a total of four statuses, they can be expressed using 2 bits. Therefore, 2''X2 = 2 K bits.

Also, the line timing display circuit 6 of the thinning control circuit 6
4, it is counted which line the current line is from the frame pulse WFP or the vertical synchronization signal WVD,
The remainder after dividing that value by 3 is output. The rest of the structure is the same as the example shown in FIG.

The signal SFP from the frame order circuit 61, the determination signal from the status determination circuit 63, and the output signal from the timing display circuit 64 are supplied to the changeover switch 57v of the thinning circuit 5, and the line address control circuit 6.
5, and the switching control of the changeover switch 57v and whether or not the signal can be output are determined by vJIil.

That is, when the number of scanning lines in one frame is an even number, control is performed as follows. In the ba+0th line of each field, the changeover switch 57V is connected to am, and the line address control circuit 65 outputs an increment signal INC, and the signal from the changeover switch f57v is output, and in the ba+1st line, the changeover switch 57V is connected to am. is set to be undefined, and the line address control circuit 65 does not output the increment signal INC and outputting the signal is also prohibited.In the 3n, 2nd line, the selector switch 57v is connected to bm, and the line address control circuit 65 The increment signal INC is outputted, and the signal from the changeover switch 57v is outputted.

Further, when the number of scanning lines in an l frame is 6 + 1, the control is performed as follows. In the field where a frame pulse exists, the changeover switch 57v is connected to bl in the ba+0th line from the frame pulse, and an increment signal is output from the line address control circuit 65, and a signal from the changeover switch 57v is output. , on the 3n111th line from the frame pulse, the changeover switch 57v is set to be undefined, and the line address control circuit 65 does not output the increment signal INC, and signal output is prohibited, and on the 3n+211th line, the changeover switch 57v is set to undefined. is connected to ell, an increment signal INC is output from the line address control circuit 65, and a signal from the changeover switch 57v is output. On the other hand, in a field where there is no frame pulse, in the 3n+0@th line from the frame pulse, the changeover switch 57v is connected to all, and the line address control circuit 65 outputs an increment signal INC from the changeover switch 57v. The changeover switch 57V is set to be undefined on the 3n101st line from the frame pulse, the increment signal INC is not outputted from the line address control circuit 65, and signal output is prohibited, and on the 3n+28th line The changeover switch 57v is connected to ba, and the line address control circuit 65 outputs an increment signal INC, and a signal from the changeover switch 57v is output.

Note that in a field where a frame pulse exists, the control may be performed as follows.

That is, on the 3n,000th line from the frame pulse, the changeover switch 57v is connected to bl, and the line address control circuit 65 outputs an increment signal to output signals from the changeover switch 57v b), etc., and the frame pulse In the an+1st line from the frame pulse, the changeover switch 57v is connected to all, and the line address control circuit 65 outputs the increment signal INC, and the signal from the changeover switch 57v is output, and in the 3n102nd line from the frame pulse, The selector switch 57v is set to be undefined, the increment signal INC is not output from the line address control circuit 65, and the output of the signal is also prohibited.

Further, when the number of scanning lines in one frame is 6+3, the control is performed as follows. frame pulse to ba
In the +0th line, the changeover switch 57v is connected to all, and the line address control circuit 65 outputs an increment signal lNC to change over the changeover switch 57v.
The signal from 3n+Ll is output from the frame pulse.
In the second line, the changeover switch 57v is set to be undefined, and the line address control circuit 65 does not output the increment signal INC, and the output of the signal is also prohibited.
In the th line, the changeover switch 57v is connected to bm, and the line address control circuit 65 outputs the increment signal INC, and the signal from the changeover switch 57v is output.

Furthermore, when the number of scanning lines in the l frame is 6+5, the control is performed as follows. In the field where the frame pulse is present, on the 3n+0th line from the frame pulse, the changeover switch 57v is connected to aIll, and an increment signal is output from the line address control circuit 65, and a signal from the changeover switch 57v is output. , on the 3n101st line from the frame pulse, the changeover switch 57v is set to be undefined, and the line address control circuit 65 does not output the increment signal INC and output of the signal is prohibited, and on the bm+2nd line, the changeover switch 57v is set to undefined. b@ and an increment signal IN from the line address control circuit 65.
C is output, and the signal from the changeover switch 57v is output. On the other hand, in a field where there is no frame pulse, in the 3n10th line from the frame pulse, the changeover switch 57v is connected to bm, and the line address control circuit 65 outputs an increment signal INC from the changeover switch 57v. The signal is output,
On the 3n101st line from the frame pulse, the changeover switch 57vζ is set to be undefined, the line address control circuit 65 does not output the increment signal INC, and signal output is prohibited, and on the bm+2nd line, the changeover switch 57v is set to cl. At the same time, an increment signal INC is output from the line address control circuit 65, and a signal from the changeover switch 57v is output.

Note that in a field where no frame pulse exists, the control may be performed as follows.

That is, on the 3n+Oth line from the frame pulse, the changeover switch 57v is connected to the b side, and the line address i! 1lJ11 times The increment signal INC is output from N65 and the signal from the changeover switch 57v is output, and at the 3n+19th line from the frame pulse, the changeover switch 57v is connected to the a side, and the line address control circuit 65 outputs the increment signal INC.
C is output and the signal from the changeover switch 57v is output, and the changeover switch 57v is made indeterminate at the 3n-102nd line from the frame pulse, and the increment signal INC is not outputted from the line address control circuit 65. Signal output is prohibited.

Next, a case where the number of scanning lines is 1/4 will be explained.

In this case, the concept when the number of scanning lines is 172 can be applied. In other words, when the number of scanning lines is 1/2, the number of scanning lines is 1/2.
/2, the same control as in the case of 1/2 is used to form a non-interlaced signal once k, and then
Arithmetic averaging is performed every two lines to reduce the number of scanning lines to 1/2.

The decimation circuit 5 and the decimation control circuit 6 for processing when the number of scanning lines is 172 are, for example, a circuit that performs arithmetic averaging processing every two lines after the changeover switch 51v in the example shown in FIG. is added and configured. As a result, a good non-interlaced signal is formed even when the number of scanning lines is 174.

In this way, the circuit shown in the example of FIG. 7 can be used in common in the case where the number of scanning lines is 1/2 and in the case where the number of scanning lines is 174.

Note that when the number of scanning lines is 1/4, the number of lines may be directly thinned out to 1/2 to obtain a non-interlaced signal, as in the case of 1/2.

As mentioned above, no matter what kind of signal the video signal SVs is, if the number of scanning lines is 1/2.1/3 or 1/4,
The thinning circuit 5 forms a non-interlaced signal.

By using the same configuration as described above, a complete non-interlaced signal can be formed even in other cases where the number of scanning lines satisfies the relationship of 1/2n and 1/3n (n is a natural number).

By the way, in the above-described control, a non-interlaced signal is formed satisfactorily regardless of the phase of the frame pulse. This means that control can start from any field, even or odd. As a result, it is possible to convert an interlaced signal to a non-interlaced signal without performing field determination of the video signal SVs using written copper.

Note that as in this example, the reference video signal SVm is NTS
When the video signal SVs is a high-definition C signal, it is desirable to reduce the number of scanning lines to 1/3. This is due to the difference in aspect ratio between NTSC and high-definition.

When a high-definition image with an aspect ratio of about 5:3 is displayed on an NTSC monitor with an aspect ratio of 4:3, with the width adjusted, the effective number of scanning lines on the screen is about 380. On the other hand, the function of the scanning line number conversion device that reduces the number of scanning lines to 1/3 makes it possible to create a non-interlaced high-definition signal with 375 scanning lines per field.

Therefore, it is desirable to reduce the number of scanning lines to ⅓.

Returning to FIG. 1, each scanning line signal of the non-interlaced signal output from the thinning circuit #i5 is written into the frame memory 7.

As mentioned above, on the writing side, field determination of the video signal SVs is not performed, and when the video signal SVs is an interlaced signal, which field is written to which field portion of the frame memory 7 is not determined. However, since the output signal of the thinning circuit 5 itself is non-interlaced, there is no need to introduce another concept of even-odd fields onto the frame memory 7, and there is no problem.

Further, 11 is an overtaking determination circuit. In this overtaking judgment time '#J11, as will be described later, based on the MSB data of the line address from the write control circuit 8 and the read control circuit 12, writing and reading of the frame memory 7 are performed to which field part respectively. It is checked whether the write field has been written, and an inversion signal INV for inverting the write field is output. Then, this inverted signal I
NV is supplied to the write control circuit 8, and the field on the write side is controlled to be inverted so that writing and reading to the same field portion of the frame memory 7 do not occur simultaneously.

The write control circuit 8 receives the synchronization signal WH as described above.
In addition to D and WVD, the write clock WCK' from the thinning circuit 5 and the line address increment f word INC from the thinning control circuit 6b).

An inverted signal INV from the overtaking determination circuit 11 is supplied, and a write address for the frame memory 7 is formed based on these signals.

FIG. 18 is a diagram showing a specific configuration example of the write control circuit 8. As shown in FIG.

In the figure, the write clock WCK from the write clock generation circuit 10 is supplied to a counter 81, and this counter 81 receives a horizontal synchronization signal W from the synchronization separation circuit 9.
HD is supplied as a reset signal. The count output of this counter 81 is then supplied to the frame memory 7 as a horizontal address.

The horizontal synchronization signal WHD from the synchronization separation circuit 9 is supplied as a clock to the counter 82, and the vertical synchronization signal WVD from the synchronization separation circuit 9 is supplied to the counter 82 as a clock.
is supplied as a reset signal. Further, one increment word INC from the thinning control circuit 6 is supplied to the counter 82 as a counter enable signal. Then, MSB-1 to LS of the count output of the counter 82
B is MSB-1 of the line address (vertical address)
- is supplied to the frame memory 7 as LSB.

Further, the MSB of the count output of the counter 82 is supplied to one input terminal of an exclusive OR circuit 83, and the inverted signal INV from the overtaking determination circuit 11 is supplied to the other input terminal of this exclusive OR circuit 83. . The output signal of this exclusive OR circuit 83 is then sent to the frame memory 7 as the MSB of the line address.
supplied to

In this case, when the inversion signal INV is supplied from the overtaking control circuit 11, the output signal of the exclusive OR circuit 83, and hence the state of the MSB of the line address, is inverted, thereby inverting the write side field. Further, when the increment signal INC is supplied from the jump control circuit 6, the counter 82 becomes ready for counting and the line address is incremented. At this time, since the write enable signal WE is supplied to the frame memory 7, the frame memory 7 becomes in a writable state.

Further, the MSB of the count output of the counter 82 is supplied to the overtaking determination circuit 11, and the overtaking determination circuit 11
As will be described later, an inverted signal INV is formed from a comparison with the MSB of the read line address.

Note that the write control circuit 8 shown in FIG. 18 is an example in which the frame memory 7 is configured using a normal RAM, but the frame memory 7 may also be configured using an IC dedicated to field memory. , in that case it can be configured more easily.

According to the write address formed by the write control circuit 8 in this manner, a non-interlaced signal is written into each field portion of the frame memory 7 as shown in FIG. For simplicity, FIG. 19 shows a case where the number of lines in the l field is nine.

Next, a description will be given of how to read out the non-interlaced signal written in the frame memory 7 in this way.

In FIG. 1, 13 is a read clock generation circuit constructed using a PLL circuit or the like. The frequency of the read clock RCK generated by the clock generation circuit 13 influences the length of the displayed screen in the horizontal direction.

This frequency is determined by taking into consideration the aspect ratio of the high-definition image and the NTSC television monitor. For example, it may be the same frequency as the write clock WCK of the frame memory 7, or it may be a frequency that is an appropriate constant multiple. good. Here, the frame memory 7 will operate as a time axis changing means, and writing and reading will operate asynchronously.

Further, for reading from the frame memory 7, a reference video signal Sv■ is used. SVm is supplied to the synchronization separation circuit 14 via the input terminal 1, and the vertical synchronization signal RVD and horizontal synchronization signal RHD are separated.

In addition, the video signal SvI is transmitted to the monitor receiver 1 during a period when the down-converted high-definition signal is not applied to the monitor receiver 18 through the fixed terminal on the S side of the changeover switch 2.
118 and has the function of masking the screen.

In other words, as mentioned above, there are only about 376 scanning lines of a down-converted high-definition signal, so NT
There is no high-definition signal during the period corresponding to the scanning line difference from the 525 scanning lines of the SC monitor.
Only during this period, the video signal SVs is displayed on the screen of the image monitor receiver 18, and unnecessary parts on the screen are masked.

In addition, when generating a mask signal separately, the first
By removing the input terminal 1 and the synchronous separation circuit 14 shown in the figure,
D% RVD may be generated directly.

Now, signals may be read from the frame memory 7 in an interlaced manner or in a non-interlaced manner. Since signals are written in the frame memory in a non-interlaced manner, when reading the signals in a non-interlaced manner, it is sufficient to read out the signals in order using RHD and RVD, and no complicated control is required.

The configuration for reading interlaced No. 13 will be described below.

When reading interlaced signals, the synchronizing signals RVD and RHD are supplied to the field determination circuit 15. In this field determination circuit 15, the synchronization signal RVD,
Based on the phase of RHD, whether the reference signal S2- is even or odd is determined. For example, if the phases of the horizontal synchronizing signal RHD and the vertical synchronizing signal RVD are
As shown in C and D of the same figure, fields that match are determined to be odd fields. A field that is shifted by 2) is determined to be an even field. In this case, as shown in FIG. 21, it is assumed that the scanning line of the even field is above the same scanning line of the odd field. Note that FIG. 21 shows a case where the number of lines in one frame is nine.

The determination signal FD from the field determination circuit 15 is supplied to the read control circuit 16. This read control circuit 16 has a synchronization signal RVD separated by a synchronization separation circuit 14.
, RHD, and a read clock RCK from the clock generation circuit 13. Then, a read address of the frame memory 7 is formed based on these, and the non-interlace signal written in the frame memory 7 is converted into an interlace signal matching the interlace order of the reference video signal SVm and read out.

Here, '1J419' is stored on the frame memory 7.
As shown in the figure, it should be noted that the scanning line signal corresponding to the first line of the even field is not written.

That is, in order to match the interlace order with the video signal SV-, the 19th v! I 1. 3. 5. ◆... in the even field, 2. in Fig. 19. 4. 6. It is necessary to read out the scanning line signals of... In this case, since two fields of non-interlaced f words have been written in the frame memory 7, it does not matter which field part is assigned to which field of the video signal SV■. That is, signals are read out alternately from the two field portions of the frame memory 7 in accordance with the field determination result of the video signal Sv■ as described above.

FIG. 22 is a diagram showing a specific example of the configuration of the read control circuit #116.

In the figure, a read clock RCK from the read clock generation circuit 13 is supplied to a counter 161.

A horizontal synchronization signal RHD from the synchronization separation circuit 14 is supplied to this counter 161 via a delay circuit 162 as a reset signal. The count output of this counter 161 is then supplied to the frame memory 7 as a horizontal address.

In this case, the horizontal synchronizing signal RHD is delayed by the time set by the horizontal level 1uyI adjustment circuit 163, and then outputted by the counter 1.
61 and the counter 161 is reset. That is, from this reset timing, reading of the frame memory 7 in the horizontal direction is started, and the display start position in the horizontal direction is determined.

Note that the delay amount is configured to be adjustable in units of, for example, one cycle of the read clock RCK. here,
As the amount of delay increases, the display position of the screen shifts to the right.

Further, the horizontal synchronization signal RHD from the synchronization separation circuit 14 is supplied to the counter 164 as a clock. This counter 164 receives a vertical synchronization signal RV from the synchronization separation circuit 14.
D is supplied as a load signal via delay circuit 162. Further, the field determination signal FD from the field determination circuit 15 is supplied to the counter 164 as the LSB of the load data. The other bits of the load data are set to a low level "O", for example.Although not mentioned above, the field determination signal FD is set to a low level "O" when the field is an odd number field, and a high level when the field is an even number field. It is said to be “1”. Then, the count output of the counter 1B4 is supplied to the frame memory 7 as MSB-1 to LSB+1 of the line address (vertical address).

Further, the field determination signal FD from the field determination circuit 15 is supplied to an inverter 166, and the output signal of this inverter 166 is the MSB and LS of the line address.
B is supplied to the frame memory 7.

In this case, since the state of the MSB of the line address changes in accordance with the field determination signal FD, reading is performed alternately from the two field portions of the frame memory 7 in accordance with the even and odd fields of the video signal SVw.

In addition, in the case of an odd field, the lower two bits of the line address are initially "Ol" and the LSB is "l".
1. 3. The scanning line signals of 5°... are read out sequentially, and on the other hand, in the case of an even field, the lower two bits of the line address are initially "10" and the LSB is fixed to "OJ", so the scanning line signals of 2. 4.
6. ... scanning line signals are sequentially read out.

In this case, the vertical synchronizing signal RVD is delayed by the time M set by the screen vertical position adjustment circuit WJ167, and then supplied to the counter 1B4, and the load data is loaded into the counter 164. That is, from this a-F timing, reading of the frame memory 7 in the vertical direction is started, and the display start position in the vertical direction of the screen is determined.

Also, the horizontal synchronization signal RHD delayed by the delay circuit 162
is supplied to a high-definition screen length creation circuit 168, and from this creation circuit 168, a signal of high level "1", for example, is supplied only during the period when the screen is displayed from the timing of the horizontal synchronization signal RHD.
During the other periods, a low level "0" signal is output. The output signal of this creation circuit 168 is then supplied to an OR circuit 160.

Also, the vertical synchronizing signal RVD delayed by the delay circuit 16δ
is supplied to the high-definition screen high-definition screen v8169, and from this creation time #iI 69, the level is high, for example, "1" only during the period when the screen is displayed from the timing of vertical synchronization No. 18 RVD, and the level is low during other periods. A signal of "0" is output. The output signal of this generation circuit 1169 is then supplied to the OR circuit 160.

Further, the MSB of the read line address output from the inverter 166 is supplied to the overtaking determination circuit 11.

Although not mentioned above, the overtaking determination circuit 11 always monitors the MSB of the read line address and the MSB of the write line address (output of the counter 82), and when these have the same polarity, a high level is set to invert the write field. An inverted signal INV is output.

Although the readout control circuit 16 in the example shown in FIG. 22 is configured using a normal RAM as the frame memory 7, it is also possible to configure the frame memory 7 using an IC dedicated to field memory. In that case, a simpler configuration can be achieved.

Returning to FIG. 1, as mentioned above, the video signal for the high-definition screen read out from the frame memory 7 is
After being converted into an analog signal by the converter 17, the changeover switch 2
is supplied to the fixed terminal of s[1. This changeover switch 2
The output signal of the OR circuit 160 of the read control circuit 16 is supplied as a switching control signal. The selector switch 2 is connected to sll when the output signal of the OR circuit 160 is at a high level "1", and is connected to m@ when the output signal is at a low level "0". As mentioned above, the output signal of the OR circuit 160 is at a high level "II+" during the display period of the high-definition screen, and only during this period, the selector switch 2 is connected to 5ill, and the frame memory 7 is connected to the reference video signal Sv. A video signal for a high-definition screen that is read out is inserted.

Further, the output signal of the changeover switch 2 is supplied to a monitor receiver 18. Here, the video signal inserted into the reference video signal SVm converts the high-definition image into an NTS
The screen switches to C and is displayed well.

Note that monitor receivers on the 1st include not only current television receivers, but also IDTV and EDTV (for example, Nikkei Electronics, September 8, 1986 issue, high-definition televisions using digital technology that are expected to become the pillars of the next generation of home appliances). In this case, as mentioned earlier, if the signals are read out non-interlaced using RHD and RVD and supplied to the monitor receiver 18, the image quality will be even higher. We can expect it to change.

In the above embodiment, the reference video signal SV- is supplied to the input terminal 1 in the form of an analog signal;
This video signal 5V11 is digitized and input to input terminal 1.
If the D/A converter 17 in FIG.
is no longer necessary, and the standard/high-definition signal is switched and guided to the monitor receiver 18 as it is as a digital signal.

This is an example of an application for effectively utilizing the present invention in a digital television. As is well known, digital television is
Since high image quality can be obtained as a DTV, EDTV, etc., the above application example is suitable for use when displaying a high-definition screen on an IDTV% EDTV.

Although the explanation is redundant, in this case, if the signal is read out from the frame memory 7 in a non-interlaced manner,
Furthermore, the effect of higher image quality can be expected.

Although the above description does not refer to the color signal, once the color signal No. 18 is demodulated to the baseband, it can be processed in exactly the same manner as described above. In this case, a suitable demodulator,
The r14 transformer will be added before and after processing. Of course, the video signal may be supplied to the monitor receiver 18 as a baseband component signal, and in this case, the RA converter is not required.

In any case, if the two color difference signals are subjected to TCI or TDM in consideration of the color signal band, etc., the memory capacity can be effectively reduced.

As described above, in this example, the high-definition video signal SVs is written in each field portion of the frame memory 7 in a non-interlaced manner regardless of whether it is interlaced or not. Based on the field determination result of the reference video signal Sv-, the high-definition screen video signal is stored from the frame memory 7 so that the high-definition screen video signal has the correct interlace order with respect to the reference video signal 5V11. The signal is read out while undergoing interlace conversion.

Therefore, according to this example, the interlace relationship between the reference video signal SV@ and the high-definition screen video signal always matches, and line flicker, 2-virtual image interference, etc. do not occur.

Furthermore, in this example, since the video signal for the high-definition screen is written in each field of the frame memory 7 in a non-interlaced manner, the write field of the frame memory and the field of the video signal SVs for the high-definition screen do not necessarily match. There's no need. and,
It is checked which field the frame memo IJ 7 is written to and read from, and the data is written to the same field part of the frame memory 7.
The field on the write side is controlled to be inverted so that reading does not occur at the same time. Therefore, boundary problems due to field misjudgment of the video signal SVs for high-definition screens do not occur.

In this way, according to this example, there is no need for field determination of the video signal SVs for a high-definition screen on the writing side.
No matter what video signal is used as the video signal SVs for a high-definition screen, it is possible to down-convert and display a good high-definition screen without image quality deterioration due to field misjudgment.

Finally, a two-screen television receiver with a built-in down converter device according to a third aspect of the present invention will be described.

In the two-screen television receiver with a built-in down converter device of this example, most of the signal processing circuits can be used in common with the down converter device described above. When the down converter device is commonly used as a two-screen television signal processing circuit, the points that need to be changed are the frequency of the write-in clock WCK, and the write range and read range of the frame memory.

First, the reason why it is necessary to change the frequency of the write clock WCK will be explained.

The reason for this is that the display area of the child screen is always smaller than the display area of the parent screen. For example, if the horizontal length of the child screen is 173 of the parent screen, the number of pixels in the horizontal direction of the child screen is also 1/3 that of the parent screen.

Correspondingly, the frequency of the write clock WCK is changed to 0. For example, in the above example, the write clock WCK
The frequency of K is 1/3 of the frequency of the read clock RCK
so that it becomes Such a change can be easily realized by changing the constants of the write clock generation circuit 10.

Next, control of the write range and read range of the frame memory 7 will be explained.

As described above, in the case of a two-screen television, the frequency of the write clock WCK is selected to be, for example, 1/3 of the frequency of the read clock RCK.

Furthermore, the number of scanning lines converted in the scanning line number conversion g position needs to be set to, for example, 1/3 of the ratio of the main screen, depending on the length of the child screen in the vertical direction. In the end, the total number of pixels on the child screen is 179, etc., of the parent screen. This means that the number of pixels actually written to the frame memory 7 and read from the frame memory 7 may be 1/9 of the parent screen.

In other words, control is performed so that only actually necessary pixels are written into a predetermined range of the frame memory 7 and read out.

The above control is performed by the function control section 19 in the example shown in FIG.

FIG. 23 shows a part of the function control section 19.

FIG. 23A shows a configuration for changing the clock frequency. Although the clock frequency is determined by the configuration of the write clock generation circuit 10, it is assumed here that a suitable voltage controlled oscillator is used. Therefore, there is a changeover switch 231 that can be switched according to the user's purpose, and a fixed voltage ff232 that changes the oscillation frequency.
．． 233 is required. Note that the output signal of the changeover switch 231 is supplied to the write clock generation circuit 10 as a control signal.

In addition, in the case of a two-screen TV, the high-definition screen length creation circuit 168, the high-definition screen height creation circuit 169, the high-definition screen horizontal position adjustment circuit 163, and the high-definition screen vertical position adjustment circuit 167 in FIG.
control the frame memory 7 according to the position of the sub-screen.
It is necessary to control the timing of reading from and switching of the changeover switch 2.

's23 Figures B and C are the screen length creation circuit 16, respectively.
8 shows a configuration for controlling the screen height creation circuit 169.

In this case, changeover switches 234, 239 are used.

Further, it is assumed that the screen length creation circuit 168 and the screen height creation circuit 169 are configured with counters, and the load data 235 to 238 are changed.

Further, although not shown, circuits for controlling the screen horizontal position adjustment circuit 163 and the screen vertical position adjustment circuit 167 are also configured in the same manner as shown in FIGS. 23B and 23C, respectively.

In addition, the above-mentioned changeover switches 231, 234, and 23
9 is configured to be switched in conjunction with the user's purpose. The changeover switches 231, 234, and 239 are connected to alg when a two-screen television is used, and connected to bll when a down converter is used, for example.

As mentioned above, with the slight addition of the function control section 19,
The down converter device functions as a two-screen television receiver with a built-in down converter device.

Note that the functions of the two-screen television receiver configured in this manner are not limited to the conventional configuration in which the NTSC child screen is included in the NTSC main screen. For example, N
It is also possible to realize a configuration in which a high-definition sub-screen is included in the TSC main screen.

Of course, since it also functions as a high-definition down converter, it is possible to display only high-definition images on the entire screen of the monitor receiver 18, depending on the user's preference.

Further, the configuration of the monitor receiver 18 is as described above, and can also be configured as an IDTV, EDTV, or the like. In this case, it is expected that both the down-converted high-definition image and the sub-screen will be of extremely high quality.

[Effects of the Invention] As explained above, the scanning line number conversion device according to the present invention can convert any signal to the number of scanning lines and obtain a non-interlaced signal without using a field determining means. Therefore, there is an advantage that there is no need to be concerned about image quality deterioration due to malfunction of the field determining means.

In addition, the down converter device according to the present invention eliminates the need for field determination on the writing side to the frame memory, so that, for example, when using any video signal for a high-definition screen, there is the problem of interlace defects due to field misjudgment. It is possible to display high-definition and high-definition images without any deterioration in image quality, without causing boundary problems.

However, with this down converter device, writing and reading to frame memory can be completely asynchronous, so for example, high-definition frame rate)
60.0OHZ and NTSC frame rate) 59.9
There is an advantage that conversion between 4 Hz and 4 Hz can be performed without requiring any additional circuitry.

Furthermore, the down converter device according to the present invention is incorporated in the
Screen television receivers have the advantage of providing many functions to users with only a small amount of additional circuitry.

[Brief explanation of drawings]

11th! I is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing the scanning line structure of interlaced signals and non-interlaced signals, and FIG. 3 is a diagram showing the principle block diagram of scanning line number conversion H position and an explanation diagram of operation. , the number of scanning lines is 172 in Figures 4 to 6.
Diagram to explain interlacing when
v! I is a configuration diagram of the thinning circuit and thinning control circuit when the number of scanning lines is 172, Figures 8 to 16 are explanatory diagrams of interlacing when the number of scanning lines is reduced to 1/3, and Figure 17 is FIG. 18 is a configuration diagram of the jump circuit and thinning control circuit when the number of scanning lines is reduced to 1/3, FIG. 18 is a configuration diagram of the write control circuit, FIG. 19 is a diagram showing the write state of the frame memory, FIG. FIG. 21 is an explanatory diagram of even/odd field determination, FIG. 22 is a block diagram of the readout wJ11 circuit, and FIG. 23 is a block diagram of a part of the function control section. 1.3... Input terminal 2... Selector switch 4... A/D converter 5... Thinning circuit 6... Thinning control circuit 7◆... Frame memory 8... Write control circuit 9 .14...Synchronization separation circuit 10...Write clock generation circuit 11...Overtaking judgment circuit 12...Reading control circuit 13...Reading clock generation circuit 15...Field judgment circuit 16...Reading Control circuit 17...D/A converter 18/◆/Monitor receiver 19...Function control section

Claims (3)

[Claims] (1) A low-pass filter that band-limits the vertical spatial frequency component of the input video signal, a thinning circuit that thins out the scanning lines of the input video signal, and a thinning circuit that thins out the scanning lines of the input video signal based on the number of scanning lines in one frame of the input video signal. A scanning line number conversion device comprising: a thinning control circuit for controlling the number of scan lines. (2) A scanning line number converter according to claim 1, a frame memory in which signals are written and read, and in which the writing and reading can be controlled asynchronously; and a frame memory capable of reading one field of signals from the frame memory. 1. A down converter device comprising: a write control means that controls not to write to the field portion until the write is completed. (3) A scanning line number conversion device according to claim 1, a frame memory in which signals are written and read, and the writing and reading can be controlled asynchronously; a write control means that controls not to write to the field portion until completion; a clock frequency; a write range of the frame memory;
A two-screen television receiver with a built-in down converter device, characterized by comprising a function switching section that controls a readout range.