JPH0362738A - Arithmetic device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to arithmetic devices, such as Reed-Solomon (Reed-Solomon).
The present invention is suitable for application to an error correction device that executes arithmetic processing using a (Solomon) code.

B Summary of the Invention The present invention provides a calculation step and calculation time for vector calculation processing by providing a multiplier and an adder for performing multiplication and addition processing on a Galois field, respectively, in the same block in an arithmetic unit. can be shortened.

C. Conventional technology Conventionally, for example, in an information transmission device, a Reed-Solomon code is added to the digital data to be transmitted before transmission, and the receiving side performs error correction on the transmitted digital data using the Reed-Solomon code. This effectively prevents transmission errors.

In an error correction device using this Reed-Solomon code, for example, a Galois field (GALO
IS field).

In such cases, vector arithmetic techniques are often used in terms of circuit scale, and multiplication and addition, which correspond to conventional operators, are treated as independent arithmetic steps, and multipliers and adders that perform multiplication and addition, respectively, are separated. By providing the calculation formula, the calculation of each calculation formula can be performed.

That is, in an error correction device that performs error correction in units of words of digital data (this is called word correction) using, for example, a Reed-Solomon code, the parameter A2 required for two-word correction is calculated using syndromes 5O5S1 and S2. Conventionally, in order to realize this operation, as shown in Fig. 4, the first and second
An error correction device f4 is used that uses multipliers 1 and 2 and an adder 3 that performs addition processing on a Galois field.

That is, in this error correction device 4, the syndromes 5O1S1 and S2 are input to the input selection circuit 7 together with the first and second register outputs R1 and R2 sent from the first and second register circuits 5 and 6, respectively. ing.

This input selection circuit 7 is controlled by a control circuit (not shown). i
1 selects any two of the syndromes So, , Sl, 32 and the register outputs R1, R2 and supplies them to the multiplier 1.2 or the adder 3, respectively.

Further, the first and second multiplication outputs M1 and M2 and addition output AD, which are the calculation results of the multiplier 1.2 and the adder 3, are input to the output selection circuit 8, respectively.

The output selection circuit 8 selects the multiplication outputs M1 and M2 and the addition output AD under the control of the control circuit and outputs them to the first or second register circuit 5 or 6, respectively.

As shown in FIG. 5, this error correction device 4 with such a configuration requires two clock cycles of the clock CK to process the equation (1), and first performs the multiplication process PRM during the first half clock cycle. is executed, and addition processing PRA is executed during the subsequent one clock period in the latter half.

That is, in the multiplication process PRM, first, the input selection circuit 7 is controlled to manually input the syndromes SO and S2 to the first multiplier 1, and input the syndromes S1 and SL to the second multiplier 2. controls the output selection circuit 8 to send the first and second multiplication outputs M1 and M2 to the first and second register circuits 5 and 6, respectively.

In the subsequent addition process PRA, first, the manual selection circuit 7 is controlled to input the register outputs R1 and R2 of the first and second register circuits 5 and 6 to the adder 3, and then the output selection circuit 8 is controlled. Then, the addition output AD is sent to the first register circuit 5, and in this way, the first register circuit 5
2, which is the result of the arithmetic processing described above for equation (1).
Parameter A2 necessary for word collection is sent out.

D Problems to be Solved by the Invention By the way, in the error correction device 4 as described above, the first and second multipliers l and 2 are used to perform multiplication on a Galois field (e.g., OF C2'). , 77 exclusive or (EOR) gates and NAN
D) 64 gates are required, whereas adder 3 is composed of only 8 exclusive or (EOR) gates.

In addition, as shown in FIG. 5(B), addition processing PRA can be processed in a fraction of a time compared to multiplication processing PRM, and multiplication processing PRM and addition processing When PRA is made into independent calculation steps, there is a problem that the loss time in addition process PRA increases and the number of calculation steps required for the entire error correction calculation increases.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose an arithmetic device that can significantly shorten the arithmetic steps and the arithmetic time of vector arithmetic processing on a Galois field.

E Means for Solving the Problem In order to solve this problem, in the present invention, in the arithmetic unit 10 that performs calculations on the Galois field, a multiplier that performs multiplication processing on the Galois field in the same block] , 2, and an adder 3 that performs addition processing on the Galois field.

By providing the multiplier 1.2 and the adder 3, each of which performs multiplication and addition processing on a Galois field, in the same block for one action, vector calculation processing can be performed within the same calculation step, In this way, the computation time for vector computation processing can be shortened.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) Structure of arithmetic device In FIG. 1, parts corresponding to those in FIG. 4 are given the same reference numerals. In FIG. It is configured to include first and second multipliers 1 and 2, and an adder 3 that performs addition processing on a Galois field.

In the case of this arithmetic device 10, a Galois field (for example, GF (2
”)) Tenal 1st, 2nd, 3rd and 4th data GA
, GB, , GC and CD, the first and second data G
A and GB are input to the first multiplier 1, respectively, and third and fourth data GC and CD are input to the second multiplier 2, respectively.

Further, the first and second multiplication outputs MIO and Mll, which are the calculation results of the first and second multipliers 1 and 2, are respectively input to the adder 3, and the addition output AD, which is the calculation result of the calculation results, is input to the adder 3.
IO is sent as the calculation output OR of the calculation device 10.

In this way, in the case of this arithmetic device 10, the arithmetic processing of the arithmetic pattern expressed by the following formula % formula % (2) can be performed in one arithmetic step for the first to fourth data GA to GD in the Galois field. It is designed to be executable.

In the case of this embodiment, the period of the clock CK is the time required for the multiplication process PRM (FIG. 5(B)) and the period of the addition process PR.
The time is selected to be longer than the time required for A plus the time required for A, thereby making it possible to execute the arithmetic processing of equation (2) in a time corresponding to I clock cycles of the clock CK.

According to the above configuration, the multiplier 1.2 and the adder 3 that perform arithmetic processing on the Galois field are provided in one block, and the first
By adding the multiplication results of the second multiplier 1.2 and the second multiplier 1.2 in the adder 3, it is possible to realize an arithmetic device that can significantly shorten the arithmetic steps and the arithmetic time.

(G2) Error correction device using an arithmetic device In FIG. 2, parts corresponding to those in FIG. Syndromes 5O1S1 and S2 are input to the input selection circuit 12.

9 This input selection circuit 12 selects any two of the syndromes So, SL, and S2 under the control of a control circuit (not shown), and selects the first and second syndromes of the arithmetic device 10.
The calculation output GR is sent out via the register circuit 13.

In the above configuration, as shown in FIG.
It is designed so that it can be executed in a clock cycle.

That is, this error correction device 11 first controls the manual selection circuit 12 to input the syndromes SO and S2 to the first multiplier 1 of the arithmetic device 10, and inputs the syndromes S1 and S1 to the second multiplier 2. Enter.

As a result, the arithmetic device 10 calculates the syndrome 5O1S1,
Substituting S2 into equation (2), the following equation GR=SOxS2+5
1xS1 . . . The calculation process expressed by (3) is executed in one calculation step = 10.

In this way, in this error correction device 11, two
A parameter A2 necessary for the word collection is obtained.

According to the above configuration, the multiplier 1.2 and the adder 3 that perform arithmetic processing on the Galois field are provided in one block, and the first
By adding the multiplication results MIO and Mll of the second multiplier 1.2 in the adder 3, an error correction device 11 capable of calculating the parameter A2 necessary for 2-word correction in one operation step is realized. can.

Furthermore, if the error correction device 11 according to the present invention is used to perform all arithmetic processing on a two-word collection, the arithmetic processing can be performed in about 15 steps shorter than in the past, reducing the computation time accordingly. obtain.

(G3) Other embodiments (1) In the embodiments described above, the arithmetic unit 10 according to the present invention is configured to perform a parameter A2 necessary for two-word collection.
Although the case where the present invention is used in the error correction device 11 that calculates the error correction device 11 has been described, the present invention is not limited to this, and can be similarly applied to arithmetic processing such as 3 word correction and 10 erasure correction, which requires a significantly larger number of operations. If used for calculations, the calculation steps and calculation time can be further shortened.

(2) In the above-described embodiment, the arithmetic device 10 according to the present invention is used to realize the arithmetic pattern described above for equation (2), but the arithmetic device 10 is not limited to this, and for example, If the third or fourth data GC or CD consisting of If it is set to "1", it can be used as an independent adder.

(3) In the above-mentioned embodiment, a case was described in which the present invention was applied to an arithmetic unit of an error correction device using a Reed-Solomon code, but the present invention is not limited to this, and performs arithmetic processing on a Galois field. It is suitable for wide application to arithmetic devices.

H Effects of the Invention As described above, according to the present invention, a multiplier and an adder that respectively perform multiplication and addition processing on a Galois field are provided in the same block, and vector calculation processing is performed in the same calculation step. By doing so, it is possible to realize an arithmetic device that can significantly shorten the arithmetic steps and the arithmetic time of vector arithmetic processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an arithmetic device according to an embodiment of the present invention, FIG. 2 is a block diagram showing an error correction device using the arithmetic device, FIG. 3 is a timing chart for explaining its operation, and FIG. FIG. 4 is a block diagram showing a conventional error correction device, and FIG. 5 is a timing chart for explaining its operation. 1.2... Multiplier, 3... Adder, 4
．． 11...Error correction device, 5.6.13...
...Register circuit, 7.12...Manual selection circuit, 8...Output selection circuit, 10...Arithmetic device. = 13-

Claims (1)

[Claims] An arithmetic device that performs arithmetic operations on a Galois field, including a multiplier that performs multiplication processing on the Galois field and an adder that performs addition processing on the Galois field in the same block. Ingredients,
An arithmetic device characterized in that vector arithmetic processing is executed within the same arithmetic step.