JPH0363227U - - Google Patents
Info
- Publication number
- JPH0363227U JPH0363227U JP12418689U JP12418689U JPH0363227U JP H0363227 U JPH0363227 U JP H0363227U JP 12418689 U JP12418689 U JP 12418689U JP 12418689 U JP12418689 U JP 12418689U JP H0363227 U JPH0363227 U JP H0363227U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- maskable interrupt
- cpu
- request signal
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Description
第１図は本考案に係るリセツト制御装置の一実
施例のブロツク図、第２図はマスク不可能な割込
み（ＮＭＩ）処理の流れを示すフローチヤートで
ある。
１……ＣＰＵシステム、２……ＣＰＵ、３……
メモリ、４……制御部、５……要因センス制御部
、６……リセツトコマンドデコード部、７……リ
セツト信号発生部、ＲＴＲ……外部からのリセツ
ト要求信号、ＲＳＴ……リセツト信号。
FIG. 1 is a block diagram of one embodiment of a reset control device according to the present invention, and FIG. 2 is a flowchart showing the flow of non-maskable interrupt (NMI) processing. 1...CPU system, 2...CPU, 3...
Memory, 4...control unit, 5...factor sense control unit, 6...reset command decoding unit, 7...reset signal generation unit, RTR...external reset request signal, RST...reset signal.
Claims (1)
システムに対してのリセツトを制御するリセツト
制御装置において、前記ＣＰＵには外部からのリ
セツト要求信号がマスク不可能な割込みとして入
力するようになつており、前記のＣＰＵは、マス
ク不可能な割込みが命令の実行中に入力したとき
には、該命令の実行終了を待つてマスク不可能な
割込みに関する処理を行ない、該マスク不可能な
割込みの要因がリセツト要求信号である場合には
システムに対してリセツト処理を行なわせるよう
になつていることを特徴とするリセツト制御装置
。 In a reset control device for controlling a reset for a system having a memory accessed by a CPU, a reset request signal from the outside is input to the CPU as a non-maskable interrupt, and the reset request signal is inputted to the CPU as a non-maskable interrupt. When a non-maskable interrupt is input during the execution of an instruction, the CPU waits for the execution of the instruction to finish before processing the non-maskable interrupt, and determines that the cause of the non-maskable interrupt is a reset request signal. 1. A reset control device, characterized in that, in certain cases, the system is made to perform a reset process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12418689U JPH0363227U (en) | 1989-10-24 | 1989-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12418689U JPH0363227U (en) | 1989-10-24 | 1989-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0363227U true JPH0363227U (en) | 1991-06-20 |
Family
ID=31672124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12418689U Pending JPH0363227U (en) | 1989-10-24 | 1989-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0363227U (en) |
-
1989
- 1989-10-24 JP JP12418689U patent/JPH0363227U/ja active Pending
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