JPH0365015B2 - - Google Patents
Info
- Publication number
- JPH0365015B2 JPH0365015B2 JP57177060A JP17706082A JPH0365015B2 JP H0365015 B2 JPH0365015 B2 JP H0365015B2 JP 57177060 A JP57177060 A JP 57177060A JP 17706082 A JP17706082 A JP 17706082A JP H0365015 B2 JPH0365015 B2 JP H0365015B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- pad
- bonding pad
- electrode
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、とくに接続用パツトを有
する半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having connection pads.
化合物半導体はその物理的特徴を生かして超高
周波素子に多く用いられている。最近その中でも
―Ｖ族２元化合物半導体であるGaAsを利用し
た電界効果トランジスタ（以下、単にFETとい
う）の発展は目ざましく、量産化が進められてい
る。この段階において、高性能でしかも信頼性が
高くさらに低価格の超高周波素子を歩留りよく得
ることが必要となつている。 Compound semiconductors are often used in ultra-high frequency devices due to their physical characteristics. Among these, the development of field effect transistors (hereinafter simply referred to as FETs) using GaAs, a V group binary compound semiconductor, has been remarkable recently, and mass production is progressing. At this stage, it is necessary to obtain high-performance, highly reliable, and low-cost ultra-high frequency devices with a high yield.
この１つの要素として、ボンデイングパツド部
において、半導体基板とボンデイングパツドメタ
ルとの密着強度をいかに上げるかということが、
歩留りを上げしかも信頼度を高めるうえで重要な
問題となつてきた。 One element of this is how to increase the adhesion strength between the semiconductor substrate and the bonding pad metal in the bonding pad part.
This has become an important issue in increasing yield and reliability.
従来、GaAsFETは次に示す工程を経て作られ
ていた。すなわち、動作層の部分にメサを形成す
る工程、次にゲートを形成する工程、次にオーミ
ツクを形成する工程（アロイも含む）、最後に、
ソース、ドレインおよびゲートのボンデイングパ
ツド部の電極メタルをGaAs基板上に形成すると
いう工程である。 Conventionally, GaAsFETs have been made through the following steps. That is, the step of forming a mesa in the active layer part, the step of forming a gate, the step of forming an ohmic (including alloy), and finally,
This is a process in which electrode metal for the source, drain, and gate bonding pads is formed on the GaAs substrate.
しかし、この方法ではボンデイングパツドが最
後の工程で形成されるため、GaAsの表面がパツ
ド形成の前工程で汚れたり、また、アロイ条件の
不安定性からGaAsの表面状態が変化したりする
ために、パツドとして強固な密着力をもつたもの
が得られにくく、ボンデイング作業時もしくはそ
の後GaAs表面から電極メタルがハガレるといつ
た問題が多発していた。 However, in this method, the bonding pad is formed in the last step, so the surface of GaAs may become contaminated in the step before forming the pad, and the surface state of GaAs may change due to instability of the alloying conditions. However, it was difficult to obtain a pad with strong adhesion, and there were many problems in which the electrode metal peeled off from the GaAs surface during or after the bonding process.
本発明の目的は密度強度の強い接続パツド電極
を有する半導体装置を提供することにある。 An object of the present invention is to provide a semiconductor device having connection pad electrodes with high density and strength.
本発明の半導体装置は半導体動作領域から延在
される電極配線層が接続パツドの上の位置してこ
れらが接続されてなる電極構造を有することを特
徴とし、この構造は接続用パツドをあらかじめ形
成し、その後半導体動作領域を接触する電極を形
成し、次にこの電極と前記接続パツドとを配線層
で接続することによつて形成される。 The semiconductor device of the present invention is characterized in that it has an electrode structure in which an electrode wiring layer extending from a semiconductor operating region is located above and connected to a connection pad, and this structure has a structure in which connection pads are formed in advance. Then, an electrode is formed to contact the semiconductor operating region, and then this electrode and the connection pad are connected through a wiring layer.
従つて本発明によれば、動作領域上の電極形成
前、すなわちアロイ工程前に接続用パツドが形成
されるので、従来に比べパツド下の汚れが極端に
少なく、清浄な表面状態にてパツドを形成でき
る。また、アロイ条件の不安定性からくる表面状
態の変化という問題もなく、密着強度の強い安定
した接続用パツド（例えばボンデイングパツド）
を形成することができる。しかもパツド形成後に
アロイ時の熱履歴がはいるため、半導体とパツド
メタルとは更によく反応し、密着強度がより向上
するという利点を引き出すこともできる。 Therefore, according to the present invention, since the connection pad is formed before the electrodes are formed on the operating area, that is, before the alloying process, there is extremely less dirt under the pad than in the past, and the pad can be used with a clean surface. Can be formed. In addition, there is no problem of changes in surface condition due to instability of alloy conditions, and it is a stable connection pad with strong adhesive strength (e.g. bonding pad).
can be formed. Moreover, since the thermal history during alloying takes place after the pad is formed, the semiconductor and the pad metal react even better, making it possible to bring out the advantage that the adhesion strength is further improved.
以下、本発明の一実施例を図面を参照して、よ
り詳細に説明する。 Hereinafter, one embodiment of the present invention will be described in more detail with reference to the drawings.
第１図及至第５図は本発明の一実施例を
GaAsFETに適用してその製造工程順に示した各
断面図である。 Figures 1 to 5 show an embodiment of the present invention.
3A and 3B are cross-sectional views shown in the order of manufacturing steps applied to GaAsFET.
第１図はGaAsFETに用いられるウエハーの動
作層の部分をメサ状に形成した後の断面構造を示
している。半絶縁性GaAs基板１０上にバツフア
ー層１１を設け、このバツフアー層の一部にメサ
が形成されている。メサ上にはGaAs動作層１２
が形成されている。（動作層の厚さはメサ形成前
にあらかじめ所望の厚さにコントロールされてい
る。）
次に第２図に示すように、フオトレジストを用
いたリフトオフ法により、ソース、ドレイン及び
ゲートの各ボンデイングパツドをTi２１、Pt２
２（Ti〓1000Å、Pt2000Å）をバツフアー上
の所定部に積層して形成する。（尚、断面構造上
ゲートのパツドは図示されていない）
次に第３図に示すように、フオトレジストを用
いたリフトオフ法により、ゲート電極となるAl
２３（Al4000Å）をメサ上に形成し、しかも
このゲート電極はバツフアー層上に以前形成され
ているゲートボンデイングパツドの一部と接続さ
れる。 FIG. 1 shows the cross-sectional structure of a wafer used in a GaAsFET after the active layer portion is formed into a mesa shape. A buffer layer 11 is provided on a semi-insulating GaAs substrate 10, and a mesa is formed in a part of this buffer layer. On the mesa is a GaAs active layer 12.
is formed. (The thickness of the active layer is controlled in advance to a desired thickness before mesa formation.) Next, as shown in Figure 2, the source, drain, and gate bonding is performed using a lift-off method using photoresist. Pads Ti21, Pt2
2 (Ti = 1000 Å, Pt 2000 Å) is laminated at a predetermined portion on the buffer. (The gate pad is not shown due to the cross-sectional structure.) Next, as shown in Figure 3, the Al
23 (Al4000 Å) is formed on the mesa, and this gate electrode is connected to a portion of the gate bonding pad previously formed on the buffer layer.
次に第４図に示すように、フオトレジストを用
いたリフトオフ法により、メサ上にソースおよび
ドレイン電極となるAuGe２４、Ni２５（AuGe
1500Å、Ni400Å）を積層して形成し、アロ
イ（430℃）を行う。 Next, as shown in FIG.
1500 Å, Ni 400 Å) and then alloyed (at 430°C).
次に第５図に示すように、フオトレジストを用
いたリフトオフ法により、メサ上に形成されたソ
ースとドレインの電極と各々のボンデイングパツ
ドとを接続するための電極配線Ti２６、Au２７
（Ti500Å、Au2000Å）を形成する。この時
同時にゲートのボンデイングパツド上にTi・Au
を形成してもよい。 Next, as shown in FIG. 5, electrode wirings Ti26 and Au27 are formed by a lift-off method using photoresist to connect the source and drain electrodes and each bonding pad formed on the mesa.
(Ti500Å, Au2000Å) is formed. At this time, Ti and Au are placed on the bonding pad of the gate at the same time.
may be formed.
以上のように、本実施例のGaAsFETによれば
電極配線はボンデイングパツドの上に形成され
（時としてこのボンデイングパツド上の電極配線
を新たなパツドとして用いてもよい）ており、し
かもこれは初期工程でアロイ工程前に、形成して
いるので、汚れが少なくしかも安定した表面状態
で形成できる。この結果、密着強度の強いパツド
が形成される。また、本方法により形成されたボ
ンデイングパツド部におけるボンデイング線の引
つぱり試験においては、従来の最終工程でパツド
を形成したものに比べ、電極ハガレが大きく低減
できたことを確認した。 As described above, according to the GaAsFET of this example, the electrode wiring is formed on the bonding pad (sometimes the electrode wiring on this bonding pad may be used as a new pad). Since it is formed in the initial process before the alloying process, it can be formed with less dirt and a stable surface condition. As a result, a pad with strong adhesive strength is formed. In addition, in a pull test of the bonding wire in the bonding pad portion formed by this method, it was confirmed that electrode peeling was significantly reduced compared to the pad formed in the conventional final step.
尚、この発明はメサ構造以外のGaAsFETにも
十分適用でき、さらに基板上ではなく絶縁膜上に
設けられるパツドにも適用できる。しかも、通常
のSi等を用いた半導体装置にも使用できる。 Note that the present invention is fully applicable to GaAsFETs other than mesa structures, and can also be applied to pads provided not on a substrate but on an insulating film. Moreover, it can also be used for semiconductor devices using ordinary Si or the like.
第１図及至第５図は本発明の一実施例をその工
程順に示した各断面図である。
１０……半絶縁性GaAs基板、１１……バツフ
アー層、１２……動作層、２１……Ti、２２…
…Pt、２３……Al、２４……AuGe、２５……
Ni、２６……Ti、２７……Au。
FIGS. 1 to 5 are cross-sectional views showing an embodiment of the present invention in the order of its steps. DESCRIPTION OF SYMBOLS 10... Semi-insulating GaAs substrate, 11... Buffer layer, 12... Operating layer, 21... Ti, 22...
...Pt, 23...Al, 24...AuGe, 25...
Ni, 26...Ti, 27...Au.
Claims (1)
し、前記半導体動作領域上にゲート電極、ソース
およびドレインのオーミツク電極をそれぞれ形成
し、前記オーミツク電極とそれぞれ接続されるボ
ンデイングパツド部をそれぞれ前記半導体層上に
形成する工程を有する半導体装置の製造方法にお
いて、前記半導体層上に前記オーミツク電極とそ
れぞれ接続される前記ボンデイングパツド部をそ
れぞれ形成した後に、前記オーミツク電極を前記
半導体動作領域に形成する工程と、その後前記オ
ーミツク電極と前記ボンデイングパツド部とを接
続する配線層を前記半導体動作領域上より前記半
導体層上に延在して形成する工程とを設けること
を特徴とする半導体装置の製造方法。1. A semiconductor operating region is formed in a part of the semiconductor layer, a gate electrode, a source and a drain ohmic electrode are respectively formed on the semiconductor operating region, and bonding pad portions connected to the ohmic electrodes are respectively formed in the semiconductor operating region. In the method of manufacturing a semiconductor device, the method includes forming the bonding pad portions on the semiconductor layer to be connected to the ohmic electrodes, and then forming the ohmic electrodes in the semiconductor operation region. and then forming a wiring layer extending from above the semiconductor operation region onto the semiconductor layer to connect the ohmic electrode and the bonding pad portion. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57177060A JPS5966173A (en) | 1982-10-08 | 1982-10-08 | Semiconductor device with connecting pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57177060A JPS5966173A (en) | 1982-10-08 | 1982-10-08 | Semiconductor device with connecting pad |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5966173A JPS5966173A (en) | 1984-04-14 |
| JPH0365015B2 true JPH0365015B2 (en) | 1991-10-09 |
Family
ID=16024418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57177060A Granted JPS5966173A (en) | 1982-10-08 | 1982-10-08 | Semiconductor device with connecting pad |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5966173A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5230162A (en) * | 1975-09-03 | 1977-03-07 | Hitachi Ltd | Semiconductor device |
| JPS54134988A (en) * | 1978-04-12 | 1979-10-19 | Mitsubishi Electric Corp | Field effect transistor of schottky barrier gate type |
-
1982
- 1982-10-08 JP JP57177060A patent/JPS5966173A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5966173A (en) | 1984-04-14 |
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