JPH0365256U - - Google Patents
Info
- Publication number
- JPH0365256U JPH0365256U JP12604689U JP12604689U JPH0365256U JP H0365256 U JPH0365256 U JP H0365256U JP 12604689 U JP12604689 U JP 12604689U JP 12604689 U JP12604689 U JP 12604689U JP H0365256 U JPH0365256 U JP H0365256U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- input
- hybrid integrated
- measuring
- measurement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Description
第1図は本発明の一実施例である混成集積回路
及びその特性調整方向を示す斜視図、第2図は特
性調整方法で使用する四端子抵抗体の原理を説明
する原理説明図、そして、第3図は従来技術によ
る混成集積回路及びその特性調整方法を示す斜視
図である。
10……回路基板、11,12……入出力電極
、13……チツプ部品、14……周辺部、15…
…基板分離用破断線、16……検出用電極、17
……測定装置、18……測定端子、19……抵抗
体。
FIG. 1 is a perspective view showing a hybrid integrated circuit according to an embodiment of the present invention and its characteristic adjustment direction, FIG. 2 is a principle explanatory diagram illustrating the principle of a four-terminal resistor used in the characteristic adjustment method, and FIG. 3 is a perspective view showing a conventional hybrid integrated circuit and a method for adjusting its characteristics. 10... Circuit board, 11, 12... Input/output electrode, 13... Chip parts, 14... Peripheral part, 15...
...Broken line for substrate separation, 16...Detection electrode, 17
...Measuring device, 18...Measurement terminal, 19...Resistor.
補正 平2.4.23
考案の名称を次のように補正する。
考案の名称 混成集積回路装置
実用新案登録請求の範囲、図面の簡単な説明を
次のように補正する。Amendment 2.4.23 Hei 2. The name of the invention is amended as follows. Title of the invention Hybrid integrated circuit device The scope of the utility model registration claims and the brief description of the drawings are amended as follows.
【実用新案登録請求の範囲】
回路基板の上に、回路パターンと、測定装置の
測定端子が接触される前記回路の入出力電極とが
形成されている混成集積回路装置において、混成
集積回路装置の完成により切断される前記回路基
板の周辺部に、前記入出力電極と導通する対をな
す他方の入出力電極を形成したことを特徴とする
混成集積回路装置。[Claims for Utility Model Registration] A hybrid integrated circuit device in which a circuit pattern and input/output electrodes of the circuit that are in contact with measurement terminals of a measurement device are formed on a circuit board. A hybrid integrated circuit device, characterized in that a pair of input/output electrodes electrically connected to the input/output electrodes are formed on a peripheral portion of the circuit board to be cut upon completion.
【図面の簡単な説明】
第1図は本考案の一実施例である混成集積回路
装置を示す斜視図、第2図はその特性の調整6を
利用し、いわゆる四端子法による抵抗の高精度測
定が行われる。この四端子法による抵抗測定は、
特に、接続線の抵抗や接触抵抗の影響を取り除く
方法として既に知られた測定法であるが、この四
端子法の概念を第2図に示す。但しここでは、便
宜上、機能トリミングにおける集積回路装置全体
での測定ではなく、一個の抵抗体20の抵抗値R
を測定する場合を例として説明する。図において
、抵抗体20の両端電極21,21に、各々2本
の測定端子18,18…が接触されている。これ
らの測定端子18,18…の内部の抵抗及び接触
抵抗はr1〜r4で表す。この図の回路において
、電圧計Vの抵抗がRに比較して十分に大きけれ
ば、電圧計Vへの導線には電流は流れない。従つ
て、前記抵抗体20の両端の電圧は、抵抗r2,
r3があつもVに等しい。また、電流導線に流れ
る電流Iは、前記抵抗体20の両端において電圧
計Vへ流れ込まないから、抵抗r1,r4があつ
ても全て電流計Aに使用する四端子抵抗体の原理
を説明する原理説明図、そして、第3図は従来技
術による混成集積回路装置を示す斜視図である。
10……回路基板、11,12……入出力電極
、13……チツプ部品、14……周辺部、15…
…基板分離用破断線、16……検出用電極、17
……測定装置、18……測定端子、19……抵抗
体。[Brief Description of the Drawings] Figure 1 is a perspective view showing a hybrid integrated circuit device which is an embodiment of the present invention, and Figure 2 is a high-precision resistor using the so-called four-terminal method using the characteristic adjustment 6. Measurements are taken. Resistance measurement using this four-terminal method is
In particular, this measurement method is already known as a method for eliminating the effects of connection wire resistance and contact resistance, and the concept of this four-terminal method is shown in FIG. However, for convenience's sake, we will not measure the entire integrated circuit device during functional trimming, but instead measure the resistance value R of one resistor 20.
This will be explained by taking as an example the case of measuring . In the figure, two measurement terminals 18, 18, . . . are in contact with electrodes 21, 21 at both ends of a resistor 20, respectively. The internal resistance and contact resistance of these measurement terminals 18, 18... are represented by r1 to r4 . In the circuit shown in this figure, if the resistance of voltmeter V is sufficiently large compared to R, no current will flow through the lead to voltmeter V. Therefore, the voltage across the resistor 20 is equal to the resistance r 2 ,
r 3 is also equal to V. Also, since the current I flowing through the current conductor does not flow into the voltmeter V at both ends of the resistor 20, we will explain the principle of a four-terminal resistor that is used for the ammeter A even if there are resistors r 1 and r 4 . FIG. 3 is a perspective view showing a conventional hybrid integrated circuit device. 10... Circuit board, 11, 12... Input/output electrode, 13... Chip parts, 14... Peripheral part, 15...
...Broken line for substrate separation, 16...Detection electrode, 17
...Measuring device, 18...Measurement terminal, 19...Resistor.
Claims (1)
置の測定端子が接触される前記回路の入出力端電
極とが形成されている混成集積回路装置において
、混成集積回路装置の完成により切断される前記
回路基板の周辺部に、前記入出力電極と導通する
対をなす他方の入出力電極を形成したことを特徴
とする混成集積回路装置。 (2) 回路基板上に形成された入出力電極に測定
装置の測定端子を接触させてその電気的特性を測
定しながら回路の特性を調整する混成集積回路の
特性調整方法において、前記回路基板上と前記混
成集積回路装置の完成後に切断される基板の周辺
部とに前記測定装置の測定端子を接触させるため
の互いに導通する対をなす入出力電極を形成し、
これら対をなす入出力端子に各々前記測定装置の
測定端子を接触させて前記混成集積回路の電気的
特性を測定しながら、その特性を調整することを
特徴とする混成集積回路装置の特性調整方法。[Claims for Utility Model Registration] (1) In a hybrid integrated circuit device in which a circuit pattern and input/output terminal electrodes of the circuit that are contacted by measurement terminals of a measurement device are formed on a circuit board, A hybrid integrated circuit device, characterized in that the other input/output electrode that is electrically connected to the input/output electrode and forms a pair is formed on a peripheral portion of the circuit board that is cut when the integrated circuit device is completed. (2) In a method for adjusting the characteristics of a hybrid integrated circuit, in which the characteristics of the circuit are adjusted while measuring the electrical characteristics of the input/output electrodes formed on the circuit board by bringing measurement terminals of a measuring device into contact with the input/output electrodes formed on the circuit board, and a peripheral portion of a substrate to be cut after completion of the hybrid integrated circuit device, forming a pair of mutually conductive input/output electrodes for contacting measurement terminals of the measurement device;
A method for adjusting characteristics of a hybrid integrated circuit device, comprising: adjusting the characteristics of the hybrid integrated circuit while measuring the electrical characteristics of the hybrid integrated circuit by bringing measuring terminals of the measuring device into contact with the input/output terminals forming the pair. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12604689U JPH0365256U (en) | 1989-10-28 | 1989-10-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12604689U JPH0365256U (en) | 1989-10-28 | 1989-10-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0365256U true JPH0365256U (en) | 1991-06-25 |
Family
ID=31673885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12604689U Pending JPH0365256U (en) | 1989-10-28 | 1989-10-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0365256U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6149470B2 (en) * | 1979-03-29 | 1986-10-29 | Ishikawajima Harima Heavy Ind | |
| JPH01143386A (en) * | 1987-11-30 | 1989-06-05 | Hitachi Condenser Co Ltd | Manufacture of printed wiring board |
-
1989
- 1989-10-28 JP JP12604689U patent/JPH0365256U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6149470B2 (en) * | 1979-03-29 | 1986-10-29 | Ishikawajima Harima Heavy Ind | |
| JPH01143386A (en) * | 1987-11-30 | 1989-06-05 | Hitachi Condenser Co Ltd | Manufacture of printed wiring board |
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