JPH0366109A - Error compensating current transformer - Google Patents
Error compensating current transformerInfo
- Publication number
- JPH0366109A JPH0366109A JP1201368A JP20136889A JPH0366109A JP H0366109 A JPH0366109 A JP H0366109A JP 1201368 A JP1201368 A JP 1201368A JP 20136889 A JP20136889 A JP 20136889A JP H0366109 A JPH0366109 A JP H0366109A
- Authority
- JP
- Japan
- Prior art keywords
- impedance
- voltage
- secondary winding
- current
- compensating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Transformers For Measuring Instruments (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の目的]
(産業上の利用分野)
本発明は、誤差補償を目的とした変流器に係り、特に能
動素子を用いて誤差補償を行なう誤差補償形変流器に関
する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a current transformer for the purpose of error compensation, and in particular to an error compensation type current transformer that compensates for errors using active elements. Concerning vessels.
(従来の技術)
第3図は従来の能動素子を用いた誤差補償形変流器であ
る。同図において1は鉄心であって、この鉄心1は1次
側に巻数N1を巻装してなる1次巻線2.2次側に巻数
N2を巻装してなる2次巻線3を備えている。4は演算
増幅器であり、これの反転入力部は2次巻線3の一方出
力端子5に、非反転入力部は2次巻線3の他方出力端子
6に接続されている。さらに、演算増幅器4の反転入力
部と出力部との間に帰還抵抗7を接続している。(Prior Art) FIG. 3 shows a conventional error compensation type current transformer using active elements. In the figure, 1 is an iron core, and this iron core 1 has a primary winding 2 wound with N1 turns on the primary side and a secondary winding 3 wound with N2 turns on the secondary side. We are prepared. 4 is an operational amplifier, the inverting input part of which is connected to one output terminal 5 of the secondary winding 3, and the non-inverting input part thereof being connected to the other output terminal 6 of the secondary winding 3. Further, a feedback resistor 7 is connected between the inverting input section and the output section of the operational amplifier 4.
8.9は変流器の出力端子であって出力電圧V。8.9 is the output terminal of the current transformer and has an output voltage V.
を発生する。なお、演算増幅器4の非反転入力部は端子
6,9に共通接続して接地状態としている。occurs. Note that the non-inverting input portion of the operational amplifier 4 is commonly connected to the terminals 6 and 9 to be grounded.
而して、第3図のような誤差補償形変流器はの関係が成
立する。但し、■1は1次巻線2の1次電流、I2は2
次巻線3の2次電流、RFは帰還抵抗7の抵抗値である
。Therefore, in the error compensation type current transformer as shown in FIG. 3, the following relationship holds true. However, ■1 is the primary current of primary winding 2, I2 is 2
The secondary current of the next winding 3, RF, is the resistance value of the feedback resistor 7.
そして、上述した如き構成の誤差補償層変流器にあって
は、2次巻線3の出力端子5,6が演算増幅器40人力
部に接続されているので、増幅器4の利得が充分大きけ
れば端子5−6間の電位e5−6はほぼ零となる。つま
り、鉄心1の2次巻線3の2次負担が零となって誤差が
改善されることになるのである。In the error compensation layer current transformer configured as described above, the output terminals 5 and 6 of the secondary winding 3 are connected to the operational amplifier 40, so if the gain of the amplifier 4 is sufficiently large, then The potential e5-6 between the terminals 5-6 becomes almost zero. In other words, the secondary load on the secondary winding 3 of the iron core 1 becomes zero, and the error is improved.
(発明が解決しようとする課題)
しかし、実際には、誤差は完全に零とならず、高精度を
必要とする変流器にあっては特に励磁電流に伴う位相角
誤差に問題があった。これは、2次巻線3の2次漏れイ
ンピーダンスおよび励磁インピーダンスの存在によるも
のと考えられる。(Problem to be solved by the invention) However, in reality, the error is not completely zero, and in current transformers that require high precision, there is a problem particularly with phase angle errors associated with excitation current. . This is considered to be due to the presence of secondary leakage impedance and excitation impedance of the secondary winding 3.
すなわち、今、第3図を等価回路で表わせば第4図のよ
うになる。第4図において3は第3図の2次巻線3に相
当し、I2はその巻線3の2次漏れインピーダンス、E
2は励磁インピーダンスによる2次誘起電圧を示してい
る。2次巻線3の出力端子5,6を短絡している短絡線
10は演算増幅器4の働きによって端子5が仮想接地さ
れるためである。従って、端子5−6間を仮想接地と考
えれば、e、−6=0となり、次式が成立する。That is, if FIG. 3 is now expressed as an equivalent circuit, it will be as shown in FIG. 4. In FIG. 4, 3 corresponds to the secondary winding 3 in FIG. 3, I2 is the secondary leakage impedance of the winding 3, and E
2 indicates a secondary induced voltage due to excitation impedance. This is because the short-circuit wire 10 that short-circuits the output terminals 5 and 6 of the secondary winding 3 causes the terminal 5 to be virtually grounded by the operation of the operational amplifier 4. Therefore, if the terminals 5 and 6 are considered to be virtual ground, e, -6=0, and the following equation holds true.
E2+12・Z2=0
、’、E2= −i 2Z2 ・・・・・・
(A)しかし、(A)式に示すように、端子5−6間を
短絡しても誤差の要因である2次続起電圧E2は完全に
零とならず、2次巻線3の2次漏れインピーダンスI2
のために、その電圧降下分の値を持ってしまうことを示
している。従って、この電圧E2によってわずかの励磁
電流が発生し、これが位相角誤差の生ずる原因となって
いる。すなわち、2次電圧e、−6を零としても、2次
続起電圧E2は零とはならずこれが誤差の原因となって
いる。E2+12・Z2=0,',E2=-i 2Z2...
(A) However, as shown in equation (A), even if the terminals 5 and 6 are shorted, the secondary electromotive force E2, which is the cause of the error, does not become completely zero, and the secondary electromotive force E2 of the secondary winding 3 Next leakage impedance I2
This shows that the voltage has a value equivalent to that voltage drop. Therefore, this voltage E2 generates a slight excitation current, which causes a phase angle error. That is, even if the secondary voltages e and -6 are set to zero, the secondary electromotive force E2 does not become zero, which causes an error.
本発明は上記に鑑みてなされたもので、その目的として
は、2次巻線の2次漏れインピーダンスに影響を受ける
ことなく誤差の改善を確実に図ることができる誤差補償
層変流器を提供することにある。The present invention has been made in view of the above, and its purpose is to provide an error compensation layer current transformer that can reliably improve errors without being affected by the secondary leakage impedance of the secondary winding. It's about doing.
[発明の構成]
(課題を解決するための手段)
上記目的を達成するため、本発明は、1次巻線および2
次巻線を有する鉄心と、2次巻線に接続され該2次巻線
の2次漏れインピーダンスに比例する補償インピーダン
スと、この補償インピーダンスから負荷側をみた電圧が
ほぼ零となるように制御する能動素子と、この能動素子
の出力に応じて前記2次漏れインピーダンスによって生
ずる電圧を相殺する相殺電圧を補償インピーダンスに発
生させるための電流を供給する補償手段とを有すること
を要旨とする。[Structure of the invention] (Means for solving the problem) In order to achieve the above object, the present invention provides a primary winding and a secondary winding.
An iron core having a secondary winding, a compensation impedance connected to the secondary winding and proportional to the secondary leakage impedance of the secondary winding, and control so that the voltage seen from the compensation impedance to the load side becomes almost zero. The gist of the present invention is to include an active element and a compensating means for supplying a current to generate a canceling voltage in the compensating impedance to cancel the voltage generated by the secondary leakage impedance according to the output of the active element.
(作用)
本発明に係る誤差補償層変流器にあっては、2次巻線に
接続された補償インピーダンスに当該2次巻線の2次漏
れインピーダンスによって生ずる電圧を相殺する相殺電
圧を発生させるための電流を、補償インピーダンスから
負荷側をみた電圧をほぼ零とする能動素子の出力に応じ
て供給する。(Function) In the error compensation layer current transformer according to the present invention, a cancellation voltage is generated in the compensation impedance connected to the secondary winding to cancel the voltage generated by the secondary leakage impedance of the secondary winding. The current for this purpose is supplied in accordance with the output of the active element that makes the voltage seen from the compensation impedance to the load side approximately zero.
(実施例) 以下、図面を用いて本発明の詳細な説明する。(Example) Hereinafter, the present invention will be explained in detail using the drawings.
第1図は本発明の一実施例に係る誤差補償層変流器の回
路図である。第1図において、Zcは補償インピーダン
ス、23は能動素子を構成する演算増幅器4の出力に応
じて補償インピーダンスZCに対し後述する相殺電圧を
発生させるための帰還電流I。を供給する電流源、9,
10は演算増幅器4の入力端子である。なお、第1図に
おいて、第3図と同一構成要素には同一符号を付して詳
細な説明を省略する。FIG. 1 is a circuit diagram of an error compensation layer current transformer according to an embodiment of the present invention. In FIG. 1, Zc is a compensation impedance, and 23 is a feedback current I for generating a later-described offset voltage for the compensation impedance ZC in accordance with the output of the operational amplifier 4 constituting an active element. a current source supplying 9,
10 is an input terminal of the operational amplifier 4. In FIG. 1, the same components as those in FIG. 3 are given the same reference numerals, and detailed explanations are omitted.
電流源23は、補償手段を構成するもので、主として相
補形に接続されたNPN)ランジスタ25およびPNP
)ランジスタ27で構成されている。すなわち、トラ
ンジスタ25および27は、そのベース端子が演算増幅
器4の出力に接続され、そのエミッタ端子が2次巻線3
の出力端子5と補償インピーダンスZ。との間に接続さ
れている一方、そのコレクタ端子がそれぞれ抵抗29お
よび31を介して所要の正電源(+ V cc)および
負電源(VER)に接続されている。The current source 23 constitutes a compensation means, and mainly includes an NPN transistor 25 and a PNP transistor connected in a complementary manner.
) consists of a transistor 27. That is, the transistors 25 and 27 have their base terminals connected to the output of the operational amplifier 4, and their emitter terminals connected to the secondary winding 3.
output terminal 5 and compensation impedance Z. while its collector terminals are connected to the required positive power supply (+V cc) and negative power supply (VER) via resistors 29 and 31, respectively.
次に、本実施例の作用を第2図に示す第1図の等価回路
を用いて説明する。なお、第2図において第4図と同一
物には同一符号をイ〈jして詳細な説明を省略する。Next, the operation of this embodiment will be explained using the equivalent circuit of FIG. 1 shown in FIG. In FIG. 2, the same parts as those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.
第2図より次式が成立する。From FIG. 2, the following equation holds true.
Io=aI、 ・・・・・
・(2)とすると、
E2=
I2 Z2 + (I2 IC) ZC+Z9−1
0・・・・・・(3)
となる。演算増幅器4の利得が充分大きいとすると、
E 9−1゜=0 ・・・・・
・(4)となり、〈3〉式は
E2 =I2 Z2 + (I2 IC)ZC−(
5)となる。なお、aは定数である。Io=aI, ・・・・・・
・Assuming (2), E2=I2 Z2 + (I2 IC) ZC+Z9-1
0...(3) Assuming that the gain of operational amplifier 4 is sufficiently large, E 9-1°=0...
・(4) becomes, and formula <3> becomes E2 = I2 Z2 + (I2 IC) ZC-(
5). Note that a is a constant.
ここで、誤差を零にするためには、その要因となるE2
を零になる必要がある。(5)式においてE2=0の条
件を求めると、
となる。但し、a>1である。すなわち、第1図に示す
構成にあって本質的に誤差を補償する場合、補償インピ
ーダンスZcの値は、(6)式で示したようにZ2/(
a−1)であればよいことになる。Here, in order to make the error zero, the factor E2
needs to become zero. In formula (5), the condition for E2=0 is determined as follows. However, a>1. That is, when essentially compensating for errors in the configuration shown in FIG. 1, the value of the compensation impedance Zc is Z2/(
a-1) is sufficient.
但し、aとしては、(2)式が成立することが条件とす
る。However, the condition for a is that equation (2) holds true.
以」二のような構成において、補償インピーダンスZc
に帰還電流I。を流し、2次漏れインピーダンスZ2に
よって発生する電圧l2Z2を打ち消し、誤差の原因で
ある2次続起電圧E2を零とすることにより本質的な誤
差補償が可能となる。In the configuration shown below, the compensation impedance Zc
The feedback current I. By causing the secondary leakage impedance Z2 to cancel the voltage l2Z2 generated by the secondary leakage impedance Z2 and making the secondary electromotive force E2, which is the cause of the error, zero, essential error compensation becomes possible.
すなわち、2次巻線3と負荷側との間に高利得の演算増
幅器4を介挿することにより、2次巻線3側から負荷側
をみた電圧をほぼ零とすることが可能となり、よって2
次巻線3と負荷側とを電気的に分離した構成とすること
ができる。これにより、補償インピーダンスZcは2次
巻線3の2次続起電圧E2および2次漏れインピーダン
スZ2によって生ずる誤差のみを補償すればよいので、
特に可変形のものを使用する必要がないばかりか、負荷
が変るたびに補償インピーダンスを可変する必要がない
。また、2次巻線3より得られた電流を高利得の演算増
幅器4で電圧に変換して出力するようにしたので、演算
増幅器4の出力をそのまま負荷に供給して使用できる。That is, by inserting a high-gain operational amplifier 4 between the secondary winding 3 and the load side, it is possible to reduce the voltage seen from the secondary winding 3 side to the load side to almost zero. 2
The secondary winding 3 and the load side can be electrically separated from each other. As a result, the compensation impedance Zc only needs to compensate for the error caused by the secondary electromotive force E2 of the secondary winding 3 and the secondary leakage impedance Z2.
In particular, there is no need to use a variable type, and there is no need to vary the compensation impedance every time the load changes. Further, since the current obtained from the secondary winding 3 is converted into a voltage by the high gain operational amplifier 4 and output, the output of the operational amplifier 4 can be directly supplied to the load for use.
さらに、2次誘起電汗E2を零にできるため、鉄心1内
部の磁束が小さくなり、変流器の小形化に寄与できる。Furthermore, since the secondary induced electric sweat E2 can be reduced to zero, the magnetic flux inside the iron core 1 is reduced, contributing to downsizing of the current transformer.
また、本質的補償を行なっているので、−次電流11が
歪波の場合にも効果がある。Moreover, since essential compensation is performed, it is effective even when the negative order current 11 is a distorted wave.
なお、本発明は上記実施例に限定されるものではないこ
とは言うまでもない。すなわち、第1図では補償インピ
ーダンスZ。は(6〉式で示されるが、2次漏れインピ
ーダンスZ2は2次巻線3の直流抵抗Y2と見なしてl
Z21−’=r2とすればとなり、補償インピーダンス
Z。は単なる抵抗RCであってもよい。また、第1図で
は(2)式の如くIに=aI2としたが、a>1であれ
ばaは任意の値でもよい。It goes without saying that the present invention is not limited to the above embodiments. That is, the compensation impedance Z in FIG. is expressed by equation (6), but the secondary leakage impedance Z2 is considered as the DC resistance Y2 of the secondary winding 3, and l
If Z21-'=r2, then compensation impedance Z. may be a simple resistor RC. Further, in FIG. 1, I is set to =aI2 as in equation (2), but a may be any value as long as a>1.
さらに、本実施例では、出力を電圧出力としているが、
電圧/電流変換回路を用いて一次電流■1に比例する電
流出力としてもよい。Furthermore, in this embodiment, the output is a voltage output, but
A voltage/current conversion circuit may be used to output a current proportional to the primary current (1).
[発明の効果コ
以」二説明したように本発明によれば、2次巻線に接続
された補償インピーダンスに当該2次巻線の2次漏れイ
ンピーダンスによって生ずる電圧を相殺する相殺電圧を
発生させるための電流を、補償インピーダンスから負荷
側をみた電圧をほぼ零とする能動素子の出力に応じて供
給するようにしたので、2次巻線の2次漏れインピーダ
ンスに影響を受けることなく誤差の改善を確実に図るこ
とができる。[Effects of the Invention] 2 As explained above, according to the present invention, a compensating impedance connected to a secondary winding generates a canceling voltage that cancels the voltage generated by the secondary leakage impedance of the secondary winding. Since the current is supplied according to the output of the active element that makes the voltage seen from the compensation impedance to the load side almost zero, the error can be improved without being affected by the secondary leakage impedance of the secondary winding. can be reliably achieved.
第1図は本発明の一実施例に係る誤差補償形変流器の回
路図、第2図は第1図の等価回路図、第3図は従来の誤
差補償形変流器の回路図、第4図は第3図の等価回路図
である。
1・・・鉄心 2・・・1次巻線3・
・・2次巻線 4・・・演算増幅器7・・
・帰還抵抗 23・・・電流源zo・・・補
償インピーダンス
Z2・・・2次漏れインピーダンス
E2・・・2次誘起電圧FIG. 1 is a circuit diagram of an error compensation type current transformer according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is a circuit diagram of a conventional error compensation type current transformer. FIG. 4 is an equivalent circuit diagram of FIG. 3. 1... Iron core 2... Primary winding 3.
...Secondary winding 4...Operation amplifier 7...
・Feedback resistance 23...Current source zo...Compensation impedance Z2...Secondary leakage impedance E2...Secondary induced voltage
Claims (1)
接続され該2次巻線の2次漏れインピーダンスに比例す
る補償インピーダンスと、この補償インピーダンスから
負荷側をみた電圧がほぼ零となるように制御する能動素
子と、この能動素子の出力に応じて前記2次漏れインピ
ーダンスによって生ずる電圧を相殺する相殺電圧を補償
インピーダンスに発生させるための電流を供給する補償
手段とを有することを特徴とする誤差補償形変流器。An iron core having a primary winding and a secondary winding, a compensation impedance connected to the secondary winding and proportional to the secondary leakage impedance of the secondary winding, and a voltage from which the voltage seen from the compensation impedance to the load side is approximately zero. and compensating means for supplying a current to generate a canceling voltage in the compensation impedance to cancel the voltage generated by the secondary leakage impedance according to the output of the active element. Features an error compensation type current transformer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1201368A JP2740012B2 (en) | 1989-08-04 | 1989-08-04 | Error compensated current transformer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1201368A JP2740012B2 (en) | 1989-08-04 | 1989-08-04 | Error compensated current transformer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0366109A true JPH0366109A (en) | 1991-03-20 |
| JP2740012B2 JP2740012B2 (en) | 1998-04-15 |
Family
ID=16439903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1201368A Expired - Lifetime JP2740012B2 (en) | 1989-08-04 | 1989-08-04 | Error compensated current transformer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2740012B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004093115A1 (en) * | 2003-04-17 | 2004-10-28 | Myongji University | Method for compensating secondary current of current transformers |
| CN106033879A (en) * | 2015-03-09 | 2016-10-19 | 西门子公司 | circuit breaker protection circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63188915A (en) * | 1987-01-30 | 1988-08-04 | Mitsubishi Electric Corp | Error-compensating current transformer |
| JPS6418207A (en) * | 1987-07-14 | 1989-01-23 | Nippon Denki Keiki Kenteisho | Current transformer device of error-compensation type |
-
1989
- 1989-08-04 JP JP1201368A patent/JP2740012B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63188915A (en) * | 1987-01-30 | 1988-08-04 | Mitsubishi Electric Corp | Error-compensating current transformer |
| JPS6418207A (en) * | 1987-07-14 | 1989-01-23 | Nippon Denki Keiki Kenteisho | Current transformer device of error-compensation type |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004093115A1 (en) * | 2003-04-17 | 2004-10-28 | Myongji University | Method for compensating secondary current of current transformers |
| US7103485B2 (en) | 2003-04-17 | 2006-09-05 | Myongji University | Method for compensating secondary current of current transformers |
| CN100419936C (en) * | 2003-04-17 | 2008-09-17 | 韩国Ied | secondary current compensation method of current transformer |
| CN106033879A (en) * | 2015-03-09 | 2016-10-19 | 西门子公司 | circuit breaker protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2740012B2 (en) | 1998-04-15 |
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