JPH0366590U - - Google Patents
Info
- Publication number
- JPH0366590U JPH0366590U JP12611889U JP12611889U JPH0366590U JP H0366590 U JPH0366590 U JP H0366590U JP 12611889 U JP12611889 U JP 12611889U JP 12611889 U JP12611889 U JP 12611889U JP H0366590 U JPH0366590 U JP H0366590U
- Authority
- JP
- Japan
- Prior art keywords
- parallel
- switching elements
- series circuit
- elements
- inverter device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Circuit Arrangements For Discharge Lamps (AREA)
Description
第1図はこの考案の第1の実施例のインバータ
装置の構成を示す回路図、第2図はこの考案の第
2の実施例のインバータ装置の構成を示す回路図
、第3図はこの考案の第3の実施例のインバータ
装置の構成を示す回路図、第4図はこの考案の第
4の実施例のインバータ装置の構成を示す回路図
、第5図はこの考案の第5の実施例のインバータ
装置の構成を示す回路図、第6図は第5の実施例
において負荷回路が高周波バラスト有する蛍光ラ
ンプである場合のプリント配線板上の部品配置の
一例を示す概略斜視図、第7図はこの考案の第6
の実施例の環形2灯用照明器具の概略断面図、第
8図はインバータ装置の提案例の回路図、第9図
は第8図の高周波ノイズに関する等価回路図であ
る。
AC……交流電源、L1……第1のインダクタ
、L2……第2のインダクタ、D1……第1のダ
イオード、D2……第2のダイオード、Q1……
第1のスイツチング素子、Q2……第2のスイツ
チング素子、D3……第3のダイオード、D4…
…第4のダイオード、C1……コンデンサ、C2
……コンデンサ、C3……第3のコンデンサ、C
4……第4のコンデンサ、LD……負荷回路。
FIG. 1 is a circuit diagram showing the configuration of an inverter device according to the first embodiment of this invention, FIG. 2 is a circuit diagram showing the configuration of an inverter device according to the second embodiment of this invention, and FIG. FIG. 4 is a circuit diagram showing the configuration of an inverter device according to the fourth embodiment of this invention. FIG. 5 is a circuit diagram showing the configuration of an inverter device according to the fourth embodiment of this invention. FIG. 6 is a schematic perspective view showing an example of the arrangement of components on a printed wiring board when the load circuit is a fluorescent lamp having a high-frequency ballast in the fifth embodiment; FIG. is the sixth part of this idea.
FIG. 8 is a circuit diagram of a proposed example of an inverter device, and FIG. 9 is an equivalent circuit diagram regarding high-frequency noise in FIG. 8. AC...alternating current power supply, L1 ...first inductor, L2 ...second inductor, D1 ...first diode, D2 ...second diode, Q1 ...
First switching element, Q2 ...Second switching element, D3 ...Third diode, D4 ...
...Fourth diode, C 1 ... Capacitor, C 2
...Capacitor, C 3 ...Third capacitor, C
4 ...Fourth capacitor, LD...Load circuit.
Claims (1)
の直列回路と第1および第2のスイツチング素子
の直列回路とを並列接続し、前記第1および第2
の整流素子と通電方向を合わせて第1および第2
のスイツチング素子に第3および第4の整流素子
をそれぞれ並列接続し、前記第1および第2の整
流素子の接続点と前記第1および第2のスイツチ
ング素子の接続点との間に交流電源および第1の
インダクタの直列回路を接続し、前記第1および
第2のスイツチング素子の直列回路に第1コンデ
ンサを並列接続し、前記第1および第2のスイツ
チング素子のいずれか少なくとも一方に負荷回路
および第2のコンデンサの直列回路を並列接続し
たインバータ装置において、 前記交流電源から前記第1および第2のスイツ
チング素子の接続点への給電路中の前記第1およ
び第2のスイツチング素子の接続点の近傍位置に
雑音防止用の第2のインダクタを介挿するととも
に、前記第1および第2のスイツチング素子に雑
音防止用の第3および第4のコンデンサをそれぞ
れ並列接続したことを特徴とするインバータ装置
。[Claims for Utility Model Registration] A series circuit of first and second rectifying elements having the same current direction and a series circuit of first and second switching elements are connected in parallel, and the first and second rectifying elements are connected in parallel.
The first and second
A third and a fourth rectifying element are respectively connected in parallel to the switching element, and an AC power supply and A series circuit of a first inductor is connected, a first capacitor is connected in parallel to the series circuit of the first and second switching elements, and a load circuit and a load circuit are connected to at least one of the first and second switching elements. In an inverter device in which a series circuit of second capacitors is connected in parallel, a connection point between the first and second switching elements in a power supply path from the AC power source to a connection point between the first and second switching elements is provided. An inverter device characterized in that a second inductor for noise prevention is inserted in a nearby position, and third and fourth capacitors for noise prevention are connected in parallel to the first and second switching elements, respectively. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12611889U JPH0366590U (en) | 1989-10-26 | 1989-10-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12611889U JPH0366590U (en) | 1989-10-26 | 1989-10-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0366590U true JPH0366590U (en) | 1991-06-27 |
Family
ID=31673956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12611889U Pending JPH0366590U (en) | 1989-10-26 | 1989-10-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0366590U (en) |
-
1989
- 1989-10-26 JP JP12611889U patent/JPH0366590U/ja active Pending
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